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ARM Cortex-A9

32-bit multicore processor developed by SR1 From Wikipedia, the free encyclopedia

ARM Cortex-A9
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The ARM Cortex-A9 MPCore is a 32-bit multi-core processor that provides up to 4 cache-coherent cores, each implementing the ARM v7 architecture instruction set.[1] It was introduced in 2007.[2]

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Features

Key features of the Cortex-A9 core are:[3]

  • Out-of-order speculative issue superscalar execution 8-stage[4] pipeline giving 8.50 DMIPS/MHz/core.
  • NEON SIMD instruction set extension performing up to 16 operations per instruction (optional).
  • High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional).
  • Thumb-2 instruction set encoding reduces the size of programs with little impact on performance.
  • TrustZone security extensions.
  • Jazelle DBX support for Java execution.
  • Jazelle RCT for JIT compilation.
  • Program Trace Macrocell and CoreSight Design Kit for non-intrusive tracing of instruction execution.
  • L2 cache controller (0–4 MB).
  • Multi-core processing.

ARM states that the TSMC 40G hard macro implementation typically operates at 2 GHz; a single core (excluding caches) occupies less than 1.5 mm2 when designed in a TSMC 65 nanometer (nm) generic process[5] and can be clocked at speeds over 1 GHz, consuming less than 250 mW per core.[2]

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Chips

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Several system on a chip (SoC) devices implement the Cortex-A9 core, including:

Systems on a chip

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See also

References

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