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Serial presence detect

Standardized way to automatically access information about a memory module From Wikipedia, the free encyclopedia

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In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin SIMMs included five pins that provided five bits of parallel presence detect (PPD) data, but the 168-pin DIMM standard changed to a serial presence detect to encode more information.[1]

When an ordinary modern computer is turned on, it starts by doing a power-on self-test (POST). Since about the mid-1990s, this process includes automatically configuring the hardware currently present. SPD is a memory hardware feature that makes it possible for the computer to know what memory is present, and what memory timings to use to access the memory.

Some computers adapt to hardware changes completely automatically. In most cases, there is a special optional procedure for accessing BIOS parameters, to view and potentially make changes in settings. It may be possible to control how the computer uses the memory SPD data—to choose settings, selectively modify memory timings, or possibly to completely override the SPD data (see overclocking).

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Stored information

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For a memory module to support SPD, the JEDEC standards require that certain parameters be in the lower 128 (or more, depending on the generation) bytes of an EEPROM located on the memory module. These bytes contain timing parameters, manufacturer, serial number and other useful information about the module. Devices utilizing the memory automatically determine key parameters of the module by reading this information. For example, the SPD data on an SDRAM module might provide information about the CAS latency so the system can set this correctly without user intervention.

The SPD EEPROM firmware is accessed using SMBus, a variant of the I2C protocol. This reduces the number of communication pins on the module to just two: a clock signal and a data signal. The EEPROM shares ground pins with the RAM, has its own power pin, and has three additional pins (SA0–2) to identify the slot, which are used to assign the EEPROM a unique address in the range 0x50–0x57. Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, CPU temperatures, and fan speeds.

Before SPD, memory chips were spotted with parallel presence detect (PPD). PPD used a separate pin for each bit of information, which meant that only the speed and density of the memory module could be stored because of the limited space for pins.

SDR SDRAM

Thumb
Memory device on an SDRAM module, containing SPD data (red circled)

The first SPD specification was issued by JEDEC and tightened up by Intel as part of its PC100 memory specification introduced in 1998.[2][3][4] Most values specified are in binary-coded decimal form. The most significant nibble can contain values from 10 to 15, and in some cases extends higher. In such cases, the encodings for 1, 2 and 3 are instead used to encode 16, 17 and 18. A most significant nibble of 0 is reserved to represent "undefined".

The SPD ROM defines up to three DRAM timings, for three CAS latencies specified by set bits in byte 18. First comes the highest CAS latency (fastest clock), then two lower CAS latencies with progressively lower clock speeds.

More information Byte, Bit ...

DDR SDRAM

The DDR DIMM SPD format is an extension of the SDR SDRAM format. Mostly, parameter ranges are rescaled to accommodate higher speeds.

More information Byte, Bit ...

DDR2 SDRAM

The DDR2 SPD standard makes a number of changes, but is roughly similar to the above. One notable deletion is the confusing and little-used support for DIMMs with two ranks of different sizes.

For cycle time fields (bytes 9, 23, 25 and 49), which are encoded in BCD, some additional encodings are defined for the tenths digit to represent some common timings exactly:

More information Hex, Binary ...
More information Byte, Bit ...

DDR3 SDRAM

The DDR3 SDRAM standard significantly overhauls and simplifies the SPD contents layout. Instead of a number of BCD-encoded nanosecond fields, some "timebase" units are specified to high precision, and various timing parameters are encoded as multiples of that base unit.[8] Further, the practice of specifying different time values depending on the CAS latency has been dropped; now there are just a single set of timing parameters.

Revision 1.1 lets some parameters be expressed as a "medium time base" value plus a (signed, −128 +127) "fine time base" correction. Generally, the medium time base is 1/8 ns (125 ps), and the fine time base is 1, 2.5 or 5 ps. For compatibility with earlier versions that lack the correction, the medium time base number is usually rounded up and the correction is negative. Values that work this way are:

More information MTB byte, FTB byte ...
More information Byte, Bit ...

The memory capacity of a module can be computed from bytes 4, 7 and 8. The module width (byte 8) divided by the number of bits per chip (byte 7) gives the number of chips per rank. That can then be multiplied by the per-chip capacity (byte 4) and the number of ranks of chips on the module (usually 1 or 2, from byte 7).

DDR4 SDRAM

The DDR4 SDRAM "Annex L" standard for SPD changes the EEPROM module used. Instead of the old AT24C02-compatible 256-byte EEPROMs, JEDEC now defines a new nonstandard EE1004 type with two pages at the SMBus level each with 256 bytes. The new memory still uses the old 0x50–0x57 addresses, but two additional address at 0x36 (SPA0) and 0x37 (SPA1) are now used to receive commands to select the currently-active page for the bus, a form of bank switching.[11] Internally each logical page is further divided into two physical blocks of 128 bytes each, totaling four blocks and 512 bytes.[12] Other semantics for "special" address ranges remain the same, although write protection is now addressed by blocks and a high voltage at SA0 is now required to change its status.[13]

Annex L defines a few different layouts that can be plugged into a 512-byte (of which a maximum of 320 bytes are defined) template, depending on the type of the memory module. The bit definitions are similar to DDR3.[12]

More information Byte, Bit ...

DDR5 SDRAM

Preliminary table for DDR5, based on JESD400-5 specification.[15]

DDR5 expands the SPD table to 1024-byte. SPD of DDR5 is using the I3C bus.

More information Byte, Bit ...
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EEPROM chip

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There are three main generations of EEPROMs as described in JEDEC standards: the 256-byte EE1002 for DDR3 and earlier, the 512-byte EE1004 for DDR4, and the 1024-byte "hub" SPD1558 for DDR5. The EE1002 is the bog-standard 24-series EEPROM. The EE1004 is the newer 34-series EEPROM and differs mainly in having a "page switch" command to allow access to its full content (among other differences). The SPD1558 is very different.

There are also thermal sensor versions of EE1002 and EE1004 but they speak the same protocol for their SPD part.

Addressing

As mentioned above SPD uses three pins for addressing up to 8 separate modules from 0 to 7. This is only correct for EE1002 and EE1004; SPD1558 uses a single pin with grounding resistors to specify the module's identity from 0 to 7.[16]:§2.7

For EE1002 and EE1004 the I2C address range is 0x50–0x57. They also use respond to 0x30–0x37 if they have not been write protected (see below). If they have an associated thermal sensor, they use 0x18–0x1F. All those values are seven-bit I2C addresses formed by a Device Type Identifier Code prefix (DTIC) with SA0-2: to read (1100) from slot 3, one uses 110 0011 = 0x33. With a final R/W bit it forms the 8-bit Device Select Code.[17]

The 5118 contains many devices. The hub itself lies at 0x50–0x57, as before. The local devices are addressed through the hub using I3C.[16]:§2.7

Write protection

The EE1002 has three layers of write protection. The hardware layer is in the form of a WC# pin; when driven low, it prevents all writes. The software layer is in the form of a few commands. Changing software write protect requires driving VHV (instead of the regular 0 or 1 logic voltages) on the address pin SA0 with specific combinations for the other SA pins. As a result there is no differentaion of slot-id.[18] The final layer is the "permanent" layer, a command that can be sent to render the first 128 bytes permanently unchangable.[19]

The EE1004 has no WC# pin or a "permanent" layer. It has four commands to separately set the write-protect status of each 64-byte slice of the device (using different ) and one to clear them all at once. These commands all require driving VHV like before.[20]

The SPD5118 has two modes of protection. In the normal operating mode with the address pin connected to GND via a resistor, protection can only be added to 64-byte slices, not removed. In the "tester" mode with the address pin connected to GND directly however, these bits can be freely removed.[16]:§2.7

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Extensions

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The JEDEC standard only specifies some of the SPD bytes. The truly critical data (for up to DDR3) fits into the first 64 bytes,[6][7][21][22][23] while some of the remainder is earmarked for manufacturer identification. However, a 256-byte EEPROM is standardized (for up to DDR3). A number of uses have been made of the remaining space.

Memory generally comes with conservative timing recommendations in the SPD ROM, to ensure basic functionality on all systems. Enthusiasts often spend considerable time manually adjusting the memory timings for higher speed. Enabling special configurations such as Intel XMP or AMD EXPO often requires additional testing to ensure system stability[24] and may void CPU warranty if used out of the manufacturer’s published specifications.[25][26][27]

Enhanced Performance Profiles (EPP)

Enhanced Performance Profiles is an extension of SPD, developed by Nvidia and Corsair, which includes additional information for higher-performance operation of DDR2 SDRAM, including supply voltages and command timing information not included in the JEDEC SPD spec. The EPP information is stored in the same EEPROM, but in bytes 99–127, which are unused by standard DDR2 SPD.[28]

More information Bytes, Size ...

The parameters are particularly designed to fit the memory controller on the nForce 5, nForce 6 and nForce 7 chipsets. Nvidia encourages support for EPP in the BIOS for its high-end motherboard chipsets. This is intended to provide "one-click overclocking" to get better performance with minimal effort.

Nvidia's name for EPP memory that has been qualified for performance and stability is "SLI-ready memory".[29] The term "SLI-ready-memory" has caused some confusion, as it has nothing to do with SLI video. One can use EPP/SLI memory with a single video card (even a non-Nvidia card), and one can run a multi-card SLI video setup without EPP/SLI memory.

An extended version, EPP 2.0, supports DDR3 memory as well.[30]

Intel Extreme Memory Profile (XMP)

A similar, Intel-developed JEDEC SPD extension was developed for DDR3 SDRAM DIMMs, later used in DDR4 and DDR5 SDRAM as well. XMP uses bytes 176–255, which are unallocated by JEDEC, to encode higher-performance memory timings.[31]

Later, AMD developed AMP, an equivalent technology to XMP, for use in its "Radeon Memory" line of memory modules optimized for use in AMD platforms.[32][33] Furthermore, motherboard developers implemented their own technologies to allow their AMD-based motherboards to read XMP profiles: MSI offers A-XMP,[34] ASUS has DOCP (Direct Over Clock Profile), and Gigabyte has EOCP (Extended Over Clock Profile).[35]

DDR3 XMP

More information DDR3 Bytes, Size ...

The header contains the following data. Most importantly, it contains a "medium timebase" value MTB, as a rational number of nanoseconds (common values are 1/8, 1/12 and 1/16 ns). Many other later timing values are expressed as an integer number of MTB units.

Also included in the header is the number of DIMMs per memory channel that the profile is designed to support; including more DIMMs may not work well.

More information DDR3 Byte, Bits ...
More information DDR3 Byte 1, DDR3 Byte 2 ...

Newer versions

DDR4 specs are not yet publicly available.

AMD Extended Profiles for Overclocking (EXPO)

AMD's Extended Profiles for Overclocking (EXPO) is a JEDEC SPD extension developed for DDR5 DIMMs to apply a one-click automatic overclocking profile to system memory.[37][38] AMD EXPO-certified DIMMs include optimised timings certified to work on Zen 4 processors.[39] Unlike Intel's closed standard XMP, the EXPO standard is open and royalty-free.[38] It can be used on Intel platforms.[38] At launch in September 2022, there are 15 partner RAM kits with EXPO-certification available reaching up to 6400 MT/s.[40]

Vendor-specific memory

A common misuse is to write information to certain memory regions to bind vendor-specific memory modules to a specific system. Fujitsu Technology Solutions is known to do this. Adding different memory module to the system usually results in a refusal or other counter-measures (like pressing F1 on every boot).

02 0E 00 01-00 00 00 EF-02 03 19 4D-BC 47 C3 46 ...........M.G.F
53 43 00 04-EF 4F 8D 1F-00 01 70 00-01 03 C1 CF SC...O....p.....

This is the output of a 512 MB memory module from Micron Technologies, branded for Fujitsu-Siemens Computers, note the "FSC" (46 53 43) string. The system BIOS rejects memory modules that don't have this information starting at offset 128h.

Some Packard Bell AMD laptops also use this method, in this case the symptoms can vary but it can lead to a flashing cursor rather than a beep pattern. Incidentally this can also be a symptom of BIOS corruption as well.[41] Though upgrading a 2 GB to a 4 GB can also lead to issues.

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Reading and writing SPD information

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Memory module manufacturers write the SPD information to the EEPROM on the module. Motherboard BIOSes read the SPD information to configure the memory controller.

Onboard SMBus

The motherboard SMBus controller is the "raw" way of accessing SPD on a memory module attached to it. Some motherboard chipsets allow selecting whether the SPD should be write protected. To allow access this way, the operating system must include SMBus support, have appropriate drivers for the EEPROMs, and the motherboard SMBus needs to be connected to the SPD EEPROMs.

  • (R) On Linux and FreeBSD, the userspace program decode-dimms provided by i2c-tools decodes and prints JEDEC standard information on any memory with SPD information in the computer. It requires the pre-DDR4 SPD it requires either the "eeprom" or the "at24" driver (24-series EEPROM). For DDR4 SPD it requires either the "eeprom" driver or the "ee1004" driver (34-series EEPROMs defined in JEDEC EE1004).[42][43] On older Linux distributions, decode-dimms.pl was available as part of lm_sensors.
    • (W) The eeprog tool from i2c-tools allows writing to 24-series EEPROMs, i.e. up to DDR3.
  • (RW) On Linux and FreeBSD, the Python script spd-eeprom reads and writes AT24 and EE1004-series EEPROMs. It only provides raw SMBus reading and writing, not decoding. Driver requirements are the same as i2c-tools.[44]
  • (R) On OpenBSD 4.3+ and NetBSD 5.0+, the spdmem(4) driver accesses the EEPROM through the SMBus to provide information about memory modules (only the JEDEC standard part).
  • (R) Coreboot reads and uses SPD information to initialize all memory controllers in a computer with timing, size and other properties. Coreboot is intended to act as a computer's firmware, replacing a BIOS (or UEFI-enabled BIOS).
  • (R) HWiNFO, CPU-Z and Speccy are Microsoft Windows programs that read and display SPD information, including XMP and other extensions.[45]
  • (RW) Thaiphoon Burner (abandonware) is a Windows program that allows reading from and writing to SPD from memory modules up to DDR4 (including XMP). SPDtool is another piece of abandonware of similar purpose.

Other SMBus features

Temperature sensor

JEDEC has standards for SMBus-addressable temperature sensors on memory strips. TS3000 is for the independent sensor for up to DDR3. TSE2002 is the combined SPD and temperature sensor for up to DDR3. TSE2004 is the combined SPD and temperature sensor for DDR4. SPD5118 is the "hub" that integrates temperature and SPD on DDR5.

RGB LED control

Some memory modules (especially on Gaming PCs)[46] support RGB LEDs that are controlled by proprietary SMBus commands. This allows LED color control without additional connectors and cables. Windows kernel drivers from multiple manufacturers required to control the lights have been exploited to gain access ranging from full kernel memory access, to MSR and I/O port control numerous times in 2020 alone.[47][48][49]

SMBIOS

The SMBIOS relays data about the memory from the BIOS to the computer. This information is accessed by the dmidecode program, which runs on Linux, FreeBSD, NetBSD, OpenBSD, BeOS, Cygwin and Solaris. Again, it accesses not the SPD information, but SMBIOS information, so data may be limited or incorrect.[50]

Ex situ SMBus

By removing the EEPROM chip and transplanting it somewhere else, one can obtain a more direct SMBus access. This helps remove the interference from chipsets.

Laptops and webcams

A not so common use for old laptops is as generic SMBus readers, as the internal EEPROM on the module can be disabled once the BIOS has read it so the bus is essentially available for use. The method used is to pull low the A0,A1 lines so the internal memory shuts down, allowing the external device to access the SMBus. Once this is done, a custom Linux build or DOS application can then access the external device. A common use is recovering data from LCD panel memory chips to retrofit a generic panel into a proprietary laptop.

A related technique is rewriting the chip on webcams often included with many laptops, as the bus speed is substantially higher. They can even be modified so that 25-series chips, commonly used in storing a motherboard's UEFI ROM, can be read and written for protection against chip failure.

On some chips it is also a good idea to separate write protect lines so that the onboard chips do not get wiped during reprogramming.

Chip generation issues

This unfortunately only works on DDR3 and below, as DDR4 uses a different chip model (34-series) to fit the 512-byte SPD (as opposed to the 256-byte of earlier generations). This chip interface (EE1004/TSE2004) divides its storage into two pages and requires a page-switch to read or write the whole chip.

Some chipsets also do not correctly negotiate the reading of 34-series EEPROM chips so they may even fail to read. The software may return a "Incompatible SMBus driver?" message in response.

DDR5 uses an even more complex design, the SPD5118 "hub" with another doubling of capacity.

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On older equipment

Some older equipment require the use of SIMMs with parallel presence detect (more commonly called simply presence detect or PD). Some of this equipment uses non-standard PD coding, IBM computers and Hewlett-Packard LaserJet and other printers in particular.

See also

References

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