时序收敛（英语：Timing closure）是现场可编程逻辑门阵列、专用集成电路等集成电路设计过程中，调整、修改设计，从而使得所设计的电路满足时序要求的过程。为了完成上述过程，工程师常常需要在电子设计自动化工具辅助下工作。“时序收敛”一词有时也用于表达这些要求最终被满足的状态。
外部链接
- PhysicalTimingClosure.Com. This article is derived from the document Timing closure （页面存档备份，存于互联网档案馆） by Alessandro Uber.
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