7 nm process

In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology.

Semiconductor device fabrication
MOSFET scaling (process nodes)
010 µm – 1971 006 µm – 1974 003 µm – 1977  1.5 µm – 1981 001 µm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2024
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
v t e

Taiwan Semiconductor Manufacturing Company (TSMC) began production of 256 Mbit SRAM memory chips using a 7 nm process called N7 in June 2016,[1] before Samsung began mass production of their 7 nm process called 7LPP devices in 2018.[2] The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at Apple's September 2018 event.[3] Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips were manufactured by TSMC.[4]

In 2017, AMD released their "Rome" (EPYC 2) processors for servers and datacenters, which are based on TSMC's N7 node[5] and feature up to 64 cores and 128 threads. They also released their "Matisse" consumer desktop processors with up to 16 cores and 32 threads. However, the I/O die on the Rome multi-chip module (MCM) is fabricated with the GlobalFoundries' 14 nm (14HP) process, while the Matisse's I/O die uses the GlobalFoundries' 12 nm (12LP+) process. The Radeon RX 5000 series is also based on TSMC's N7 process.

Since at least 1997, however, "node" has become a commercial name for marketing purposes[6] that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[7][8][9] TSMC and Samsung's 10 nm (10 LPE) processes are somewhere between Intel's 14 nm and 10 nm processes in transistor density.