Capacitance–voltage profiling
Technique for characterizing semiconductor materials and devices / From Wikipedia, the free encyclopedia
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Capacitance–voltage profiling (or C–V profiling, sometimes CV profiling) is a technique for characterizing semiconductor materials and devices. The applied voltage is varied, and the capacitance is measured and plotted as a function of voltage. The technique uses a metal–semiconductor junction (Schottky barrier) or a p–n junction[1] or a MOSFET to create a depletion region, a region which is empty of conducting electrons and holes, but may contain ionized donors and electrically active defects or traps. The depletion region with its ionized charges inside behaves like a capacitor. By varying the voltage applied to the junction it is possible to vary the depletion width. The dependence of the depletion width upon the applied voltage provides information on the semiconductor's internal characteristics, such as its doping profile and electrically active defect densities.[2], [3] Measurements may be done at DC, or using both DC and a small-signal AC signal (the conductance method [3], [4]), or using a large-signal transient voltage.[5]