Project Denver

Project Denver is the codename of a central processing unit designed by Nvidia that implements the ARMv8-A 64/32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation (dynamic recompilation) where "Denver's binary translation layer runs in software, at a lower level than the operating system, and stores commonly accessed, already optimized code sequences in a 128 MB cache stored in main memory".^[2] Denver is a very wide in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).

Nvidia Denver 1/2

General information
Launched	2014 (Denver) 2016 (Denver 2)
Designed by	Nvidia
Cache
L1 cache	192 KiB per core (128 KiB I-cache with parity, 64 KiB D-cache with ECC)
L2 cache	2 MiB @ 2 cores
Architecture and classification
Technology node	28 nm (Denver 1) to 16 nm (Denver 2)
Instruction set	ARMv8-A
Physical specifications
Cores	2

Nvidia Carmel

General information
Launched	2018
Designed by	Nvidia
Max. CPU clock rate	to 2.3 GHz
Cache
L1 cache	192 KiB per core (128 KiB I-cache with parity, 64 KiB D-cache with ECC)
L2 cache	2 MiB @ 2 cores
L3 cache	(4 MiB @ 8 cores, T194[1])
Architecture and classification
Technology node	12 nm
Instruction set	ARMv8.2-A
Physical specifications
Cores	2

For the Soviet HIV disinformation campaign, see Operation Denver.

Project Denver is targeted at mobile computers, personal computers, servers, as well as supercomputers.^[3] Respective cores have found integration in the Tegra SoC series from Nvidia. Initially Denver cores was designed for the 28 nm process node (Tegra model T132 aka "Tegra K1"). Denver 2 was an improved design that built for the smaller, more efficient 16 nm node. (Tegra model T186 aka "Tegra X2").

In 2018, Nvidia released an improved design (codename: "Carmel", based on ARMv8 (64-bit; variant: ARM-v8.2^[1] with 10-way superscalar, functional safety, dual execution, parity & ECC) got integrated into the Tegra Xavier SoC offering a total of 8 cores (or 4 dual-core pairs).^{[4][failed verification]} The Carmel CPU core supports full Advanced SIMD (ARM NEON), VFP (Vector Floating Point), and ARMv8.2-FP16.^[1] First published testings of Carmel cores integrated in the Jetson AGX development kit by third party experts took place in September 2018 and indicated a noticeably increased performance as should expected for this real world physical manifestation compared to predecessors systems, despite all doubts the used quickness of such a test setup in general an in particular implies.^[5] The Carmel design can be found in the Tegra model T194 ("Tegra Xavier") that is designed with a 12 nm structure size.

Overview

• Pipelined in-order superscalar processor
• 2-way decoder for ARM instructions
• On-the-fly binary translation of ARM code into internal VLIW instructions by hardware translator, uses software emulation as fallback
• Translation can reorder ARM instructions, and remove ones that do not contribute to the result^[2]
• Up to 7 micro-ops per clock cycle with translated VLIW instructions; cannot run simultaneously with ARM decoder
• L1 cache: 128 KiB instruction + 64 KiB data per core (4-way set associative)
• 2 MiB shared L2 cache between two Denver cores (16-way set-associative)^[6]
• Denver also sets aside 128 MiB of main memory to store translated VLIW code; this part of memory is inaccessible to the main operating system.
• Up to 2.5 GHz clockspeeds on TSMC 28 nm process^[7]

Chips

A dual-core Denver CPU was paired with a Kepler-based GPU solution to form the Tegra K1; the dual-core 2.3 GHz Denver-based K1 was first used in the HTC Nexus 9 tablet, released November 3, 2014.^[8][9] Note, however, that the quad-core Tegra K1, while using the same name, isn't based on Denver.

The Nvidia Tegra X2 has two Denver2 cores paired with four Cortex-A57 cores using a coherent HMP (Heterogeneous Multi-Processor Architecture) approach.^[10] They are paired with a Pascal GPU.

The Tegra Xavier has a Volta GPU and several special purpose accelerators. The 8 Carmel CPU cores is divided into 4 ASIC macro blocks (each having 2 cores,) matched to each other with a crossbar and 4 MiB of shared L3 memory.

History

The existence of Project Denver was revealed at the 2011 Consumer Electronics Show.^[11] In a March 4, 2011 Q&A article CEO Jen-Hsun Huang revealed that Project Denver is a five-year 64-bit ARMv8-A architecture CPU development on which hundreds of engineers had already worked for three and half years and which also has 32-bit ARM instruction set (ARMv7) backward compatibility.^[12] Project Denver was started in Stexar Company (Colorado) as an x86-compatible processor using binary translation, similar to projects by Transmeta. Stexar was acquired by Nvidia in 2006.^[13][14][15]

According to Tom's Hardware, there are engineers from Intel, AMD, HP, Sun and Transmeta on the Denver team, and they have extensive experience designing superscalar CPUs with out-of-order execution, very long instruction words (VLIW) and simultaneous multithreading (SMT).^[16]

According to Charlie Demerjian, the Project Denver CPU may internally translate the ARM instructions to an internal instruction set, using firmware in the CPU.^[17] Also according to Demerjian, Project Denver was originally intended to support both ARM and x86 code using code morphing technology from Transmeta, but was changed to the ARMv8-A 64-bit instruction set because Nvidia could not obtain a license to Intel's patents.^[17]

The first consumer device shipping with Denver CPU cores, Google's Nexus 9, was announced on October 15, 2014. The tablet was manufactured by HTC and features the dual-core Tegra K1 SoC. The Nexus 9 was the first 64-bit Android device available to consumers.^[18]

See also

• Comparison of ARMv8-A cores