ARM Cortex-A520

The ARM Cortex-A520 is a "little" CPU core model from Arm^[1] unveiled in TCS23 (total compute solution) it serves as a successor to the CPU core ARM Cortex-A510^[2]. The Cortex-A5xx CPU cores series generally focus on high efficiency, the CPU core can be paired with the other CPU cores in its family like ARM Cortex-A720 or/and Cortex-X4 in a CPU cluster.^[3]

ARM Cortex-A520

General information
Launched	2023
Designed by	ARM Ltd.
Performance
Max. CPU clock rate	1.8 GHz  to 2.27 GHz
Cache
L1 cache	64/128 KiB (32/64 KiB I-cache with parity, 32/64 KiB D-cache) per core
L2 cache	0–512 KiB per complex
L3 cache	256 KiB – 32 MiB (optional)
Architecture and classification
Microarchitecture	ARM Cortex-A520
Instruction set	ARMv9.2-A
Products, models, variants
Product code name	Hayes
History
Predecessor	ARM Cortex-A510
Successor	ARM Cortex-A530

Improvements

• 8% peak performance improvement over the Cortex-A510^[4]
• Support only 64-bit applications
• Up to 512 KiB of private L2 cache (From 256 KiB)
• Add QARMA3 Pointer Authentication (PAC) algorithm support
• Update to ARMv9.2^[5]

Architecture comparison

"LITTLE" core

uArch	Cortex-A53	Cortex-A55	Cortex-A510	Cortex-A520	Cortex-A530
Codename	Apollo	Ananke	Klein	Hayes	Nevis
Peak clock speed	2.3 GHz	2.1 GHz	2.0 GHz	2.0 GHz	-
Architecture	ARMv8.0-A	ARMv8.2-A	ARMv9.0-A	ARMv9.2-A
AArch	32-bit and 64-bit			64-bit
Branch predictor history (entries)	3072[6]	-
Max In-flight	None (In-order)
L0 (Mops entries)	None
L1-I + L1-D	8/64+8/64 KiB	16/64+16/64 KiB	32/64+32/64 KiB		-
L2	0–256 KiB		0–512 KiB		-
L3	None	0–4 MiB	0–16 MiB	0–32 MiB	-
Decode Width	2		3	3 (2 ALU)	-
Dispatch	8[7]

See also

• ARM Cortex-X4, related high performance microarchitecture
• ARM Cortex-A720, related efficient sustained performance microarchitecture
• Comparison of ARMv8-A cores, ARMv8 family