ARM Cortex-A76

The ARM Cortex-A76 is a central processing unit (CPU) core implementing the 64-bit ARMv8.2-A architecture, designed by Arm Holdings' design center in Austin, Texas. Compared to its predecessor, the Cortex-A75, ARM claimed performance improvements of up to 25% in integer operations and 35% in floating-point operations.^[2]

ARM Cortex-A76

General information
Launched	2018[1]
Designed by	ARM Holdings
Performance
Max. CPU clock rate	to 3 GHz in phones, 3.3 GHz in tablets/laptops
Address width	40-bit
Cache
L1 cache	128 KiB (64 KiB D-cache and 64 KiB I-cache with parity) per core
L2 cache	128–512 KiB per core
L3 cache	512 KiB–4 MiB (optional)
Architecture and classification
Instruction set	ARMv8-A: A64, A32, T32
Extensions	ARMv8.1-A, ARMv8.2-A, ARMv8.3-A,[a] ARMv8.4-A,[b] Cryptography, RAS
Physical specifications
Cores	1–4
Co-processor	ARM Cortex-A55 (optional)
Products, models, variants
Product code name	Enyo
Variant	Arm Neoverse N1
History
Predecessors	ARM Cortex-A75 ARM Cortex-A73 ARM Cortex-A72
Successor	ARM Cortex-A77

Design

The Cortex-A76 is a successor to both the Cortex-A73 and Cortex-A75, though it is based on an entirely new microarchitecture. It features a 4-wide decode, out-of-order, superscalar pipeline. The frontend can fetch and decode four instructions per cycle and dispatch up to four macro-operations and eight micro-operations per cycle. The out-of-order execution window includes 128 entries. The backend includes eight execution ports, with a pipeline depth of 13 stages and execution latencies of 11 stages.^[2][3]

The Cortex-A76 supports unprivileged 32-bit applications, but privileged software, such as operating systems and kernels, must use the 64-bit ARMv8-A instruction set.^[4] Additional features include support for ARMv8.3-A's LDAPR instructions, ARMv8.4-A's dot product instructions, and ARMv8.5-A's speculative execution controls such as SSBS, CSDB, SSBB, and PSSBB.^[5]

Memory bandwidth is improved by up to 90% over the Cortex-A75.^[6][7] ARM targeted the Cortex-A76 for high-performance computing, including Windows 10 laptops,^[8] positioning it as a competitor to Intel’s Kaby Lake architecture.^[9]

The Cortex-A76 also supports ARM DynamIQ technology, and is often paired with energy-efficient Cortex-A55 cores in multi-core configurations.^[2]

Usage

The Cortex-A76 is available as a semiconductor intellectual property core (SIP core) and can be licensed by manufacturers for integration into custom system on a chip (SoC) designs. It is commonly combined with other components such as graphics processing units (GPUs), digital signal processors (DSPs), and image signal processors (ISPs) on a single chip.

The Cortex-A76 first appeared in the HiSilicon Kirin 980 SoC.^[10] The company's later Kirin 985 and 990 series of SoCs would also use the A76.

ARM collaborated with Qualcomm on semi-custom versions of the Cortex-A76 used in several of its Kryo CPU designs, including the Kryo 495 (Snapdragon 8cx), Kryo 485 (Snapdragon 855/855 Plus), Kryo 470 (Snapdragon 730), and Kryo 460 (Snapdragon 675). Qualcomm made several architectural modifications, such as increasing the reorder buffer to expand the out-of-order execution window.^[11]

Other SoCs using the Cortex-A76 include:

• Broadcom BCM2712 SoC (2023) with four A76 cores. Used in the Raspberry Pi 5.^[12]
• Intel Agilex D-series SoC FPGAs^[13]
• MediaTek Helio G90, G90T, G95, G99, and Dimensity 800 and 820^[14][15][16]
• Rockchip RK3588 and RK3588S (2020)
• Samsung Exynos 990 and Exynos Auto V9^[17]

See also

• Comparison of ARM processors

Notes

1. LDAPR instructions
2. Dot product instructions