Bluespec

Bluespec, Inc. is an American semiconductor device electronic design automation company based in Framingham, Massachusetts, and co-founded in June 2003 by computer scientists Arvind Mithal, professor of the Massachusetts Institute of Technology (MIT), and Joe Stoy of Oxford University. Arvind had formerly founded Sandburst in 2000, which specialized in producing chips for 10 Gigabit Ethernet (10GE) routers, for this task.^[1][2]

Bluespec has two product lines which are primarily for application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) hardware designers and architects. Bluespec supplies high-level synthesis (electronic system-level (ESL) logic synthesis) with register-transfer level (RTL). The first Bluespec workshop was held on August 13, 2007, at MIT.^[3]

Bluespec SystemVerilog

Bluespec

Bluespec

Paradigm	Functional
Family	Verilog, Haskell
Developer	Bluespec Inc.
Stable release	Version 2022.01 / January 2022[4]
Scope	HDL
Filename extensions	.bsv
Website	bluespec.com
Major implementations
Bluespec Compiler (BSC); Toy Bluespec Compiler
Dialects
SystemVerilog (BSV), Haskell (BH: Bluespec Classic)

Arvind had developed the Bluespec language named Bluespec SystemVerilog (BSV), a high-level functional programming hardware description programming language which was essentially Haskell extended to handle chip design and electronic design automation in general.^[5][6] The main designer and implementor of Bluespec was Lennart Augustsson. Bluespec is partially evaluated (to convert the Haskell parts) and compiled to the term rewriting system (TRS). It comes with a SystemVerilog frontend.^[7] BSV is compiled to the Verilog RTL design files.

Tools

BSV releases are shipped with the following hardware development kit:^[8]: 7

BSV compiler

The compiler takes BSV source code as input and generates a hardware description for either Verilog or Bluesim as output. It was opensourced by Bluespec inc. in 2020 under New BSD License terms.

Libraries

BSV is shipped with a set programming idioms and hardware structures

Verilog modules

Several primitive BSV elements, such as first in, first out (FIFOs) and processor registers, are expressed as Verilog primitives.

Bluesim

A cycle simulator for BSV designs.

Bluetcl

A collection of Tcl extensions, scripts, and packages to link into a Bluespec design.