The Compact Model Coalition[1] (formerly the Compact Model Council)[2] is a working group in the electronic design automation (EDA) industry formed to choose, maintain and promote the use of standard semiconductor device models.[3] Commercial and industrial analog simulators (such as SPICE) need to add device models as technology advances (see Moore's law) and earlier models become inaccurate. Before this group was formed, new transistor models were largely proprietary, which severely limited the choice of simulators that could be used.
It was formed in August, 1996, for the purpose developing and standardizing the use and implementation of SPICE models and the model interfaces. In May 2013, the Silicon Integration Initiative (Si2) and TechAmerica announced the transfer of the Compact Model Council to Si2 and a renaming to Compact Model Coalition.[4]
To develop and maintain the models, the CMC works with device modeling and simulation experts belonging to an international collection of universities and research institutions. In alphabetical order, the present development organizations are Auburn University (SiGe group),[5] CEA-LETI, Hiroshima University (HiSIM Research Center),[6] Macquarie University, TU Dresden (HiCUM development),[7] UC Berkeley (BSIM Group),[8] and University of Waterloo (WEIS Group).[9] Though the development is done at these different institutions, all of them follow the same Verilog-A coding standards[10] and QA standards, and they all go through a common beta testing and release process.[11] CMC maintains a workgroup for each standardized model, composed of interested industry members and the model developers.
Most of the CMC development is industry-funded, supported by dues from CMC member companies. The member companies primarily are silicon design companies, silicon foundry companies, Integrated Device Manufacturers (IDM), and silicon design EDA companies.
Production releases of industry-funded CMC models are available to the public free of charge. The CMC member companies have access to earlier pre-production versions of those models, and they have the opportunity to help direct the evolution of those models.
The industry-funded CMC models, listed alphabetically, are:
More information Model Name, Developer ...
| Model Name |
Developer |
Description |
|---|
| ASM-ESD[12] |
Macquarie University |
Advanced SPICE models for ESD diodes |
| ASM-HEMT[13] |
Macquarie University |
Advanced SPICE models for High Electron Mobility GaN HEMT Transistors. The physical model is surface potential based and is computationally efficient by virtue of being completely analytical. It includes velocity saturation effects, access region resistance effects, DIBL, temperature dependence and models for gate current and noise. |
| BSIM-Bulk (and BSIM4)[14][15] |
UC Berkeley |
BSIM (Berkeley Short Channel IGFET Mode)-BULK is a new surface potential based Bulk MOSFET model. It features model symmetry valued for analog and RF applications while maintaining the strong support and performance of the BSIM model valued for all applications since 1996. |
| BSIM-CMG[16] |
UC Berkeley |
BSIM-CMG (Common Multi-Gate) models 3D multi-gate devices where the multiple gate surfaces act electrically as a single gate |
| BSIM-IMG[17] |
UC Berkeley |
BSIM-IMG (Independent Multi-Gate) models the electrical characteristics of the independent double-gate structures like Ultra-Thin Body and BOX SOI (Silicon on Insulator) transistors (UTBB). |
| BSIM-SOI[18] |
UC Berkeley |
Standard model for planar SOI (Silicon on Insulator) devices. The foundation of this model is the BSIM3[19] framework. A newer version based on surface potential concepts is also being released which ensures complete model symmetry. |
| HICUM_L0[20] |
ADM Enterprises (TU Dresden) |
High CUrrent Model for bipolar transistors. It addresses modern BJT and HBT technologies by including more accurate modeling than the Gummel-Poon model for important physical effects such as forward transit time, base-collector punch-through and collector impact ionization. Compared to HiCUM_L2, HiCUM_L0 targets faster simulation speed, so it gives up some accuracy at high frequencies and high current densities. |
| HICUM_L2[20] |
ADM Enterprises (TU Dresden) |
HICUM stands for HIgh CUrrent Model and targets the design of bipolar transistor circuits at high-frequencies and high-current densities using a wide range of Si, SiGe or III-V based process technologies. HICUM_L2 is an advanced physics-based compact model that contains accurate formulations of all known physical effects, enables geometry scaling and statistical modeling, and covers a wide temperature, operating and frequency range. |
| HiSIM2[21] |
Hiroshima University |
HiSIM (Hiroshima University STARC IGFET Model) is a surface-potential based MOSFET model based on the drift diffusion approximation. |
| HiSIM_HV[22] |
Hiroshima University |
HiSIM-HV is for accurate modeling of high-voltage MOSFETs |
| HiSIM_SOI[23] |
Hiroshima University |
HiSIM_SOI is a surface-potential-based SOI MOSFET model for circuit simulation based on the drift-diffusion approximation |
| HiSIM_SOTB[24] |
Hiroshima University |
HiSIM_SOTB accurately models the ultra-thin-body SOI MOSFET, a practical transistor structure for super-low power consumption. |
| L_UTSOI[25] |
CEA-LETI |
L-UTSOI ("L" for LETI, from CEA-LETI) is dedicated to ultra-thin-body Fully Depleted SOI (FDSOI) technologies. The L-UTSOI model is able to physically describe FDSOI transistor behavior for any bias configuration, including the case of strong forward back bias where two channels exist at the front and back interfaces of a thin silicon body. |
| MEXTRAM[26] |
Auburn University |
MEXTRAM is an advanced compact model for the description of bipolar transistors. It contains many features that the widely-used Gummel-Poon model lacks. Mextram can be used for advanced processes like double-poly or even SiGe transistors, for high-voltage power devices, and even for uncommon situations like lateral NPN-transistors in LDMOS technology. |
| MVSG[27] |
MIT, U. of Waterloo |
The MVSG model is a physical model for GaN HEMTs that includes formulations for currents and charges that can be used for GaN-based circuit simulations, in particular RF- and HV-applications. |
| PSP[28] |
CEA-LETI |
PSP is a surface-potential-based MOS model containing all relevant physical effects (mobility reduction, velocity saturation, DIBL, gate current, lateral doping effects, STI stress, etc.) to model present-day and upcoming deep-submicron bulk CMOS technologies. Development of this model started with NXP and University of Arizona, then University of Delft, and now CEA-LETI in France. |
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To address the increasing need for Reliability (ageing) simulation the CMC nominated the OMI Interface[29] as the new EDA vendor independent solution for ageing simulations. Technically the Interface is very close the TMI2 Interface developed by TSMC. The standardization will allow Silicon Foundries to develop a common set of aging models that will work with all significant analog simulators.
The CMC also has released a Verilog-A code recommended best practices document (“CMC Policy on Standardization of Verilog-A Model Code”)[10] and a Verilog-A Linter program called VAMPyRE (Github link) which can be freely accessed to help increase the quality of model code for all model developers worldwide.
The CMC continues to evaluate new models for standardarization. New models are submitted to the Coalition, where their technical merits are discussed, and then potential standard models are voted on.
In 2025, the CMC has started a new initiative and is setting up and running the first International Compact Modeling Conference (ICMC),[30] to be held on June 26-June 27 in San Francisco, co-located with the DAC 2025 conference.