Version 2.0 introduces new generalized information blocks primarily intended for UltraHD High Dynamic Range (HDR) displays, such as LCD computer monitors and LCD/OLED televisions with native support for BT.2100 color space and PQ/HLG transfer functions. It also makes optional predefined CRT/LCD timings from DMT and CEA-861 standards, switching to formula-based structures which follow VESA CVT-RB and GTF.
The base DisplayID 2.0 variable-length structure is the same for all data blocks:
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Each data block starts with mandatory block tag, revision number (0-7), and payload length (0-248) bytes, and has a variable length of up to 251 bytes. The following blocks are currently defined:
0x20 Product identification
0x20
Product identification block contains standard vendor and product IDs, serial number, date of manufacture and product name.
Comparing to legacy block 0x00
, Microsoft ISA Plug&Play identifier is replaced with IEEE OUI, first used in the network MAC address.
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Product Identification block[2]
Byte offset | Bit/value | Description/format |
0 | 0x20 | Product Identification block tag |
1 | 0 | Revision |
2 | 12–248 | Number of payload bytes |
3–5 | | Manufacturer/Vendor ID IEEE Organizationally Unique Identifier (OUI) |
6–7 | | Product ID, LSB/MSB |
8–11 | | Serial number, optional |
12 | 0–51, 255 | Week of Manufacture (0 =unspecified); Model year tag (255 ) |
13 | 0, 15–255 | Year of Manufacture/Model Year (0 =unspecified); Stored Value = (Year-2000) |
14 | 1–236 | Length of product name string |
15–251 | | Product name string, optional |
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0x21 Display parameters
0x21
Display parameters block contains basic parameters such as viewable area size and pixel count, supported color depth, and factory calibrated RGB color space, white point, luminance, and gamma transfer function.
Comparing to legacy block 0x01
, color calibration values have been moved here from block 0x02
and max/min luminance values have been added. Display size can be specified in 1 mm increments in addition to default 0.1 mm.
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Display Parameters block[2]
Byte offset | Bit/value | Description/format |
0 | 0x21 | Display parameters block tag |
1 | Bits 2:0 = 0 | Revision |
Bit 7 | Image size precision:
0 = 0.1 mm (default)
1 = 1 mm
|
2 | 29 | Number of payload bytes |
3–4 | | Horizontal image size |
5–6 | | Vertical image size |
7–8 | | Horizontal pixel count |
9–10 | | Vertical pixel count |
11 | Feature-support flags |
Bits 2:0 | Scan orientation:
0 = Left–right, top–bottom (default)
1 = Right–left, top–bottom
2 = Top–bottom, right–left
3 = Bottom–top, right–left
4 = Right–left, bottom–top
5 = Left–right, bottom–top
6 = Bottom–top, left–right
7 = Top–bottom, left–right
|
Bits 4:3 | Max luminance information:
0 = non-zero values are a guaranteed minimum
1 = non-zero values are a guidance for the source device
|
Bit 6 | Color-space information:
0 = uses CIE 1931 (x,y) coordinates (default)
1 = uses CIE 1976 (u',v') coordinates
|
Bit 7 | Audio speakers information:
0 = integrated (default)
1 = external jack
|
12–14 | Primary Color 1 Chromaticity |
Bits 7:0 | x/u' value, 8-bit LSB |
Bits 11:8 | x/u' value, 4-bit MSB |
Bits 15:12 | y/v' value, 4-bit LSB |
Bits 23:16 | y/v' value, 8-bit MSB |
15–17 | | Primary color 2 chromaticity |
18–20 | | Primary color 3 chromaticity |
21–23 | | White point chromaticity |
24–25 | | Max luminance (full coverage), cd/m2 |
26–27 | | Max luminance (10% coverage), cd/m2 |
28–29 | | Min luminance, cd/m2 |
30 | Color-depth, display-technology flags |
Bits 2:0 | Color Depth:
0 = not defined
1 = 6 bpc
2 = 8 bpc
3 = 10 bpc
4 = 12 bpc
5 = 16 bpc
|
Bits 6:4 | Display technology:
0 = not specified
1 = AMLCD
2 = AMOLED
|
31 | | Gamma EOTF (1.00–3.54), stored value = (Gamma × 100) – 100 = (Gamma – 1) × 100 (255 =unspecified) |
Notes: Chromaticity values use 12-bit fractional integer numbers (bit12 × 2−1 + ... + bit0 × 2−12)
Luminance values use 16-bit IEEE 754-2008 half-precision floating-point format (−0 = not used) |
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0x22 Type VII detailed timings
0x22
Detailed timing block type VII defines CTA-861 compatible timings based on pixel rate. This block is based on type VI block 0x13
.
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Type VII – Detailed timing block header[2]
Byte offset | Bit/value | Description/format |
0 | 0x22 | Detailed timing block tag |
1 | Bits 2:0 | Revision: 0 , 1 |
Bit 2 | DSC support
0 = Standard descriptor
1 = Descriptors with DSC pass-through (block revision 1)
|
2 | 20–240 | Number of payload bytes (N × 20, 1 ≤ N ≤ 12) |
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More information Byte offset, Bit/value ...
Type VII Detailed timing descriptor[2]
Byte offset | Bit/value | Description/format |
0–2 | Pixel Clock, kHz (0.001–16,777.216 MPix/s) |
Bits 7:0 | 8-bit LSB |
Bits 15:8 | 8-bit middle bits |
Bits 23:16 | 8-bit MSB |
3 | Timing options |
Bits 3:0 | Aspect ratio:
0 = 1:1
1 = 5:4
2 = 4:3
3 = 15:9
4 = 16:9
5 = 16:10
6 = 64:27
7 = 256:135
8 = Calculate using horizontal/vertical active image pixels/lines (bytes 4-5 and 12–13)
|
Bit 4 | Frame scanning type:
0 = progressive
1 = interlaced
|
Bits 6:5 | Stereoscopic 3D:
0 = mono timing
1 = 3D stereo timing
2 = mono or 3D stereo depending on user action
|
Bit 7 | Preferred timing:
1 = preferred detailed timing
|
4–5 | | Horizontal active image pixels |
6–7 | | Horizontal blank pixels |
8–9 | Horizontal offset (front porch) |
Bits 7:0 | 8-bit LSB |
Bits 14:8 | 7-bit MSB |
Bit 15 | Horizontal sync polarity:
0 = negative
1 = positive
|
10–11 | | Horizontal sync width |
12–13 | | Vertical active image lines |
14–15 | | Vertical blank lines |
16–17 | Vertical sync offset (front porch) |
Bits 7:0 | 8-bit LSB |
Bits 14:8 | 7-bit MSB |
Bit 15 | Vertical sync polarity:
0 = negative
1 = positive
|
18–19 | | Vertical Sync Width |
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0x23 Type VIII enumerated timing code
0x23
Type VIII enumerated timing code block is based on type IV DMT ID block 0x06
. It provides one-byte or two-byte video mode codes as defined in VESA Display Monitor Timings standard or Video Information Codes defined by CTA-861 and HDMI.
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Type VIII – Enumerated timing code header[2]
Byte offset | Bit/value | Description/format |
0 | 0x23 | Enumerated timing code block tag |
1 | Bits 2:0 = 0 | Revision |
Bit 3 | Timing code size:
0 = one-byte descriptor
1 = two-byte descriptor
|
Bits 7:6 | Timing code type:
0 = DMT
1 = CTA VIC code
2 = HDMI VIC code
|
2 | 1–248 | Number of payload bytes |
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0x24
Type IX formula-based timings block is based on type V short timings block 0x11
.
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Type IX – Formula-based timing header[2]
Byte offset | Bit/value | Description/format |
0 | 0x24 | Formula-based timing block tag |
1 | Bits 2:0 = 0 | Revision |
2 | 6–248 | Number of payload bytes (N × 6) |
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Type IX Formula-based timing descriptor[2]
Byte offset | Bit/value | Description/format |
0 | Timing options |
Bits 2:0 | Timing Formula/Algorithm
0 = CVT
1 = CVT-RB
2 = CVT-R2
|
Bit 3 | NTSC Video optimized refresh rate × (1000/1001):
0 = not supported
1 = supported
|
Bits 6:5 | Stereoscopic 3D:
0 = Mono timing
1 = 3D stereo timing
2 = Mono or 3D stereo depending on user action
|
1–2 | | Horizontal active image pixels |
3–4 | | Vertical active image lines |
5 | | vertical refresh rate, Hz (1-256) |
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0x25 Dynamic video timing range
0x25
Dynamic video timing range block is based on block 0x9h
Video Timing Range Limits; the new version allows more precise definition of pixel rate in 1 kHz steps and adds indication for variable refresh rates.
More information Byte offset, Bit/value ...
Dynamic video timing range block[2]
Byte offset | Bit/value | Description/format |
0 | 0x25 | Dynamic video timing range block tag |
1 | Bits 2:0 | Revision: 0 , 1 |
2 | 9 | Number of payload bytes |
3–5 | | Minimum pixel clock, kHz |
6–8 | | Maximum pixel clock, kHz |
9 | | Minimum vertical refresh rate, Hz |
10 | | Maximum vertical refresh rate LSB, Hz |
11 | Dynamic video timing range Support Flags |
Bits 1:0 | Maximum vertical refresh rate MSB, Hz (block revision 1) |
Bit 7 | Seamless dynamic video timing change:
0 = not supported
1 = supported with fixed horizontal pixel rate and dynamic vertical blanking
|
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0x26 Display interface features
0x26
Display interface features block describes color depth, dynamic range, and transfer function supported by the display controller. It is based on blocks 0x0F
display interface features and 0x02
color characteristics.
More information Byte offset, Bit/value ...
Display Interface Features block[2]
Byte offset | Bit/value | Description/format |
0 | 0x26 | Display interface features block tag |
1 | Bits 2:0 = 0 | Revision |
2 | 9 | Number of payload bytes |
3 | Color-depth support, RGB encoding |
Bit 0 | 6 bpc |
Bit 1 | 8 bpc |
Bit 2 | 10 bpc |
Bit 3 | 12 bpc |
Bit 4 | 14 bpc |
Bit 5 | 16 bpc |
0 = no support
1 = supported
|
4 | Color-depth support, YCbCr 4:4:4 encoding |
5 | Color-depth support, YCbCr 4:2:2 encoding |
Bit 0 | 8 bpc |
Bit 1 | 10 bpc |
Bit 2 | 12 bpc |
Bit 3 | 14 bpc |
Bit 4 | 16 bpc |
0 = no support
1 = supported
|
6 | Color-depth support, YCbCr 4:2:0 encoding |
7 | Minimum pixel rate for YCbCr 4:2:0 encoding, pixel rate = 74.25 MP/s × Stored Value (0 =supported at all modes) |
8 | Audio capability and feature support flags |
Bit 5 | 48 kHz sample rate |
Bit 6 | 44.1 kHz sample rate |
Bit 7 | 32 kHz sample rate |
0 = no support
1 = supported
|
9 | Color space and EOTF combination 1 |
Bit 0 | sRGB (IEC 61966-2-1) Color space and EOTF |
Bit 1 | ITU-R BT.601 Color space and EOTF |
Bit 2 | ITU-R BT.709 Color space and ITU-R BT.1886 EOTF |
Bit 3 | Adobe RGB Color space and EOTF |
Bit 4 | DCI-P3 (SMPTE RP 431–2) Color space and EOTF |
Bit 5 | ITU-R BT.2020 Color space and EOTF |
Bit 6 | ITU-R BT.2020 Color space and SMPTE ST 2084 EOTF |
0 = no support
1 = supported
|
10 | 0 | Color space and EOTF combination 2: reserved |
11 | 0–7 | Number of additional color space and EOTF bytes (N) |
11+#N | Additional color space and EOTF byte #N |
Bits 3:0 | EOTF:
0 = defined by display interface rules
1 = sRGB (IEC 61966-2-1)
2 = ITU-R BT.601
3 = ITU-R BT.1886 for ITU-R BT.709
4 = Adobe RGB
5 = DCI-P3 (SMPTE RP 431–2)
6 = ITU-R BT.2020
7 = Gamma function (value stored in Display Parameters byte 31)
8 = SMPTE ST 2084
9 = Hybrid log–gamma
10 = Custom (details defined in another block)
|
Bits 3:0 | Color space:
0 = Undefined – follow display interface rules
1 = sRGB (IEC 61966-2-1)
2 = ITU-R BT.601
3 = ITU-R BT.709
4 = Adobe RGB
5 = DCI-P3 (SMPTE RP 431–2)
6 = ITU-R BT.2020
7 = Custom (details defined in another block)
|
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0x27 Stereo display interface
0x27
Stereo display interface block is based on block 0x10
and describes stereoscopic 3D/VR modes (i.e. timings codes and stereo frame formats) supported by the display.
More information Byte offset, Bit/value ...
Stereo Display Interface block[2]
Byte offset | Bit/value | Description/format |
0 | 0x27 | Stereo Display Interface block tag |
1 | Bits 2:0 | Revision: 0 , 1 |
Bits 7:6 | Stereoscopic 3D Timing:
0 = 0b00 = block applies to all 3D timings
1 = 0b01 = block applies to 3D timings with specified Timing Code (block revision 1 )
2 = 0b10 = block applies to all timings in any timing block
3 = 0b11 = block applies to timings with specified Timing Code (block revision 1 )
|
2 | (N+2) | Number of payload bytes |
3 | (N+1) | Number of bytes in Stereo Interface Method block |
4 | | Stereo Interface Method code:
0 = Frame/Field Sequential (N=1)
1 = Side-by-Side (N=1)
2 = Pixel Interleaved (N=8)
3 = Dual Interface (N=1)
4 = Multi-view (N=2)
5 = Stacked Frame (N=1)
255 = Vendor defined (N=0)
|
5 | Stereo Interface Method-specific Parameters (N bytes) |
5+N | 3D Timings descriptor 1
|
Bits 4:0 | Timing Code number (M1, 1-31) |
Bits 7:6 | Timing Code Type:
0 = DMT
1 = CTA VIC code
2 = HDMI VIC code
|
(6+N+#M1) | One-byte Timing Code #M1 |
(7+N+M1) | 3D Timings descriptor 2
|
(6+N+M1+#M2) | One-byte Timing Code #M2 |
Note: 3D Timings descriptors only exist when byte 1 bit 6 = 1 |
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More information N, Bytes, Bit/value ...
Stereo Display Interface Method-specific Parameters[2]
N, Bytes | Bit/value | Description/format |
1 | Method code: 0 = Frame/Field Sequential |
Bit 0 | Stereo Polarity:
0 = Stereo Sync on left eye image
1 = Stereo Sync on right eye image
|
1 | 1 = Side-by-Side |
Bit 0 | View Identify:
0 = Left half represents left eye image
1 = Left half represents right eye image
|
8 | 2 = Pixel Interleaved |
Bits 7:0 | Interleave pattern – 8x8 bit mask
0 = Pixel position for right eye image
1 = Pixel position for left eye image
|
1 | 3 = Dual Interface |
Bit 0 | Interface Left and Right Polarity:
0 = Interface carries right eye image
1 = Interface carries left eye image
|
Bits 2:1 | Mirroring
0 = No mirroring
1 = Left/Right are mirrored
1 = Top/Bottom are mirrored
|
2 | 4 = Multi-view |
| Number of Views |
| View Interleaving Method Code |
1 | 5 = Stacked Frame |
Bit 0 | View Identity:
0 = Top is left-eye image, bottom is right-eye image
|
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0x28 Tiled display topology
0x28
Tiled display topology block describes displays that consist of multiple physical display panels, each driven by a separate video interface. It is based on block 0x12
.
More information Byte offset, Bit/value ...
Tiled Display Topology block[2]
Byte offset | Bit/value | Description/format |
0 | 0x28 | Tiled Display Topology block tag |
1 | Bits 2:0 = 0 | Revision |
2 | 22 | Number of payload bytes |
3 | Tiled Display and Tile Capabilities |
Bits 2:0 | Tile Behavior when the only tile being transmitted:
0 = None of the following
1 = Display at Tile Location (byte 5)
2 = Scale to fit the display
3 = Clone to other tiles
|
Bits 4:3 | Tile Behavior when N tiles (1 < N < Max, N<>2) are being transmitted:
0 = None of the following
1 = Display at Tile Location (byte 5)
|
Bit 6 | Tile Bezel Descriptor:
0 = Not available
1 = Available at bytes 11-15
|
Bit 7 | Physical Display Enclosure:
0 = Multiple physical enclosures
1 = Single physical enclosure
|
4–6 | Tiled Display Topology and Tile Location |
4 | Total Number of Tiles |
Bits 3:0 | Number of Vertical Tiles, 4-bit LSB |
Bits 7:4 | Number of Horizontal Tiles, 4-bit LSB |
5 | Tile Location |
Bits 3:0 | Vertical Tile Location, 4-bit LSB |
Bits 7:4 | Horizontal Tile Location, 4-bit LSB |
6 | Tile Location and Total Number of Tiles |
Bits 1:0 | Vertical Tile Location, 2-bit MSB |
Bits 3:2 | Horizontal Tile Location, 2-bit MSB |
Bits 5:4 | Number of Vertical Tiles, 2-bit MSB |
Bits 7:6 | Number of Horizontal Tiles, 2-bit MSB |
7–10 | Tile Size |
Bits 7:0 | Horizontal Size, 8-bit LSB |
Bits 15:8 | Horizontal Size, 8-bit MSB |
Bits 23:16 | Vertical Size, 8-bit LSB |
Bits 31:24 | Vertical Size, 8-bit MSB |
11–15 | Tile Pixel Multiplier and Tile Bezel-related Information |
11 | | Tile Pixel Multiplier |
12 | | Tile Top Bezel Size |
13 | | Tile Bottom Bezel Size |
14 | | Tile Right Bezel Size |
15 | | Tile Left Bezel Size |
Note: Tile Bezel in pixels = (Tile Pixel Multiplier × Tile Bezel Size × 0.1) |
16–24 | Tiled Display Topology ID |
16–18 | | Tiled Display Manufacturer/Vendor ID IEEE Organizationally Unique Identifier (OUI) |
19–20 | | Tiled Display Product ID LSB/MSB |
21–24 | | Serial number, optional |
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0x29 Container ID
0x29
Container ID block defines a unique identifier used to associate additional devices that may be present in a multifunctional display.
More information Byte offset, Bit/value ...
ContainerID block[2]
Byte offset | Bit/value | Description/format |
0 | 0x29 | ContainerID block tag |
1 | Bits 2:0 = 0 | Revision |
2 | 16 | Number of payload bytes |
3–18 | Bits 128:0 | ContainerID Universally Unique Identifier (UUID) |
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0x7E Vendor-specific data
0x7E
Vendor-specific data includes proprietary parameters which are not supported by DisplayID 2.0 structures.
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Vendor-specific data block[2]
Byte offset | Bit/value | Description/format |
0 | 0x7E | Vendor-specific block tag |
1 | Bits 2:0 | Revision |
2 | 3–248 | Number of payload bytes |
3–5 | | Manufacturer/Vendor ID IEEE Organizationally Unique Identifier (OUI) |
6–224 | | Payload bytes |
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More information Byte offset, Bit/value ...
VESA Vendor-specific data block[2]
Byte offset | Bit/value | Description/format |
0 | 0x7E | Vendor-specific block tag |
1 | Bits 2:0 = 1 | Revision |
2–4 | 0x3A0292 | VESA OUI |
5 | Bits 2:0 | Structure type:
0 = Embedded DisplayPort (eDP)
1 = External DisplayPort
|
Bit 7 | Default Color space and EOTF handling:
0 = interpret "RGB unspecified color space" as sRGB Color space and EOTF
1 = interpret as "native" color space, EOTF is specified in the Display Parameters block 0x21
|
6 | Bits 3:0 | Number of horizontal pixels overlapping an adjacent panel segment: 0-8
|
Bits 6:5 | Multi-SST operation:
0 = 0b00 = not supported (Conventional Single-Stream Transport)
1 = 0b01 = two streams (two or four links)
2 = 0b10 = four streams (four links)
|
7 | Bits 5:0 | Pass-through timing, integer target DSC bpp (bits per pixel) |
8 | Bits 3:0 | Pass-through timing, fractional target DSC bpp (bits per pixel) |
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0x81 CTA DisplayID
0x81
CTA DisplayID block provides information on CTA-861 EDID timings.
More information Byte offset, Bit/value ...
CTA DisplayID block header[2]
Byte offset | Bit/value | Description/format |
0 | 0x81 | CTA DisplayID block tag |
1 | Bits 2:0 = 0 | Revision |
2 | 3–248 | Number of payload bytes |
3 | CTA Block 1 Tag Code and Block 1 Length |
Bits 4:0 | Block 1 Length (L1) |
Bits 7:5 | Tag code (CTA-861-G) |
4-L1 | CTA Block 1 Descriptor #L1 |
(L1+2) | | CTA Block 2 Tag Code and Block 2 Length |
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