Elmore delay

Elmore delay is a simple approximation to the delay through an RC network in an electronic system. It is often used in applications such as logic synthesis, delay calculation, static timing analysis, placement and routing, since it is simple to compute (especially in tree structured networks, which are the vast majority of signal nets within IC's) and is reasonably accurate ^[1]. Even where it is not accurate, it is usually faithful, in the sense that reducing the Elmore delay will almost always reduce the true delay, so it is still useful in optimization.

Elmore delay can be thought of in several ways, all mathematically identical.

• For tree structured networks, find the delay through each segment as the R (electrical resistance) times the downstream C (electrical capacitance). Sum the delays from the root to the sink.
• Assume the output is a simple exponential, and find the exponential that has the same integral as the true response. This is also equivalent to moment matching with one moment, since the first moment is a pure exponential.
• Find a one pole approximation to the true frequency response. This is a first-order Padé Approximation.

There are many extensions to Elmore delay. It can be extended to upper and lower bounds ^[2] to include inductance as well as ${\displaystyle R}$ and ${\displaystyle C}$, to be more accurate (higher order approximations). ^[3]

Application in circuit modelling

A simple interconnect (wire) between two components can be modeled as an RC ladder network. If the wire is divided into ‘${\displaystyle N}$’ segments, each consisting of resistance ‘${\displaystyle R}$’ and capacitance ‘${\displaystyle C}$’, the resulting circuit is of order ${\displaystyle N}$. Using a first-order Padé approximation, the complex circuit can be reduced to a single equivalent resistance ${\displaystyle R_{\text{eq}}}$ and capacitance ${\displaystyle C_{\text{eq}}}$. The time constant of this first-order system is ${\displaystyle R_{\text{eq}}*C_{\text{eq}}}$, which represents Elmore delay.

Calculating Elmore delay

Consider a simple wire connecting two nodes namely A and B as shown in Fig.1., the Elmore delay (${\displaystyle T_{D}}$) from A to B is calculated as follows.

Fig.1. RC model of a simple wire connecting node A and B.

${\displaystyle T_{D}=R_{1}C_{1}+(R_{1}+R_{2})C_{2}+(R_{1}+R_{2}+R_{3})C_{3}+(R_{1}+R_{2}+R_{3}+R_{4})(C_{4}+C_{Inp_{B}})}$

More generally, for a interconnect modelled with '${\displaystyle n}$' series RC network,

the Elmore Delay (${\displaystyle T_{D}}$) is given by ${\displaystyle \sum _{i=1}^{n}\left(\sum _{j=1}^{i}R_{j}\right)C_{i}}$

and the 50% output propagation delay is given by ${\displaystyle \ln(2)\cdot T_{D}}$.

Types of Elmore delay

Elmore delay is commonly divided into two components for simplicity: intrinsic and extrinsic Elmore delay. Intrinsic Elmore delay arises from the parasitic resistance and capacitance of the interconnect itself, while extrinsic Elmore delay is attributed to the loading network, typically modeled as the input capacitance of loading network at node B (denoted as C_{Inp_B}​).

Intrinsic and Extrinsic Elmore delay denoted by ${\displaystyle T_{\text{Intrinsic}}}$ and ${\displaystyle T_{\text{Extrinsic}}}$ of the RC network in Fig.1. are given as follows,

${\displaystyle T_{\text{Intrinsic}}=R_{1}C_{1}+(R_{1}+R_{2})C_{2}+(R_{1}+R_{2}+R_{3})C_{3}+(R_{1}+R_{2}+R_{3}+R_{4})C_{4}}$

${\displaystyle T_{\text{Extrinsic}}=(R_{1}+R_{2}+R_{3}+R_{4})C_{Inp_{B}}}$

Therefore total Elmore delay: ${\displaystyle T_{D}=T_{\text{Intrinsic}}+T_{\text{Extrinsic}}}$

Elmore delay of branching RC networks

To calculate the Elmore delay of a branching RC network, the capacitances on branches that do not lie along the signal path to the output are lumped at the corresponding branch points on the main path. The Elmore delay is then computed as if it were a simplified RC network.

Fig.2., Branching RC network.

In Fig. 2, to calculate the Elmore delay from node A to node B, the resistances ${\displaystyle R_{5},R_{6}}$, and ${\displaystyle R_{7}}$ in the branching network are ignored. However, the capacitances ​${\displaystyle C_{5},C_{6}}$, and ${\displaystyle C_{7}}$in the branching path C are lumped at the branching node on the main signal path, effectively placed in parallel with capacitance ${\displaystyle C_{2}}$​. This simplification allows the Elmore delay to be calculated using the simplified RC network.

Therefore, Elmore Delay from A to B denoted by ${\displaystyle T_{D_{A-B}}}$ is as follows,${\displaystyle T_{D_{A-B}}=R_{1}C_{1}+(R_{1}+R_{2})(C_{2}+C_{5}+C_{6}+C_{7})+(R_{1}+R_{2}+R_{3})C_{3}+(R_{1}+R_{2}+R_{3}+R_{4})C_{4}}$

Similarly, to calculate the Elmore Delay from A to C, the resistances ${\displaystyle R_{3}}$and ${\displaystyle R_{4}}$ are ignored and capacitance ${\displaystyle C_{3}}$ and ${\displaystyle C_{4}}$are lumped into the branching node, and we simply find the delay of simple RC network from A to C.

Elmore Delay from node A to C (${\displaystyle T_{D_{A-C}}}$) is given by,${\displaystyle T_{D_{A-C}}=R_{1}C_{1}+(R_{1}+R_{2})(C_{2}+C_{3}+C_{4})+(R_{1}+R_{2}+R_{5})C_{5}+(R_{1}+R_{2}+R_{5}+R_{6})C_{6}+(R_{1}+R_{2}+R_{5}+R_{6}+R_{7})C_{7}}$

Techniques to reduce Elmore delay

A straightforward method to reduce (intrinsic) Elmore delay is to insert buffers along long interconnects. This breaks the RC network into smaller segments, thereby lowering the overall delay.

From the above equations, it is clear that the Elmore delay between two logic gates connected by a simple wire is mainly caused by the parasitic resistance of the wire. The resistance R of a wire is given by ${\displaystyle R=\rho {\frac {L}{A}}}$

where ρ is the resistivity, L is the wire length, and A is the cross-sectional area. Since resistance is inversely proportional to the cross-sectional area, increasing A reduces the resistance. However, increasing the cross-sectional area also increases the capacitance, given by ${\displaystyle C={\frac {\varepsilon _{0}A}{d}}}$

where ε₀​ is the permittivity and d is the separation distance.

To effectively reduce Elmore delay, the wire geometry can be optimized as shown in Fig.3.. A commonly used technique is wire tapering, where the wire’s cross-sectional area is larger near the driver and tapers down towards the load. This design balances the trade-off between resistance and capacitance, minimizing their combined effect and reducing overall delay more efficiently ^[4].

Fig.3. Tapered wire connecting driver (root) and load (sink).

Limitations of delay optimization techniques

With shrinking semiconductor technology nodes, the number of metal layers available for routing increases. However, routing signals from the upper metal layers down to the silicon to insert buffers requires multiple via's. These via's consume valuable routing resources, introduce additional parasitic' s along the path, and can block other signal routes, leading to congestion.

Similarly, wire tapering can cause routing congestion and poor track utilization because the varying cross-sectional area reduces available routing space. This non-uniformity makes it difficult to route other wires in the remaining spacing. Additionally, for interconnects related to power delivery, the thinner wire sections introduced by tapering increase the risk of electromigration ^[5], which may lead to physical wire damage and long-term reliability issues.

See also

• Static timing analysis
• William Cronk Elmore
• Transmission line
• RC time constant