System performance

The AURIX family devices range from a 300 MHz three-core device with 8MB embedded Flash down to 130 MHz and 80 MHz single-core and single core lockstep devices with 1.5MB, 1MB and 0.5MB of embedded Flash. The package portfolio includes a BGA-516 package with a ball-compatible BGA-292 package (I/O subset), and compatible QFP-176, QFP-144, QFP‑100 to QFP-64 packages.

TRICOR DSP functionality

Multicore
TriCore with up to 300 MHz per core
1.7–2.4 DMIPS/MHz
DSP with up to 1.8 GFLOPS
Supports floating point and fixed point operations with all cores
Fast Fourier accelerator
Pixel Preprocessor
Embedded EEPROM^{[dubious – discuss]}
Generic Timer Module (GTM)
Advanced timer unit for totally flexible PWM generation and hardware input capture
Redundant flexible 12-bit ADC
Delta sigma converters
Single supply 5V or 3.3V
Availability of AUTOSAR 4.x and 3.2.1
Ta = -40 °C ... 145 °C

Safety Features

The AURIX architecture has been developed according to an audited ISO26262-compliant process and designed to meet ASIL-D on an application level. The platform uses up to 2 cores in TriCore lockstep mode, a lockstep architecture combined with safety technology such as internal communication buses or distributed memory protection systems. Hardware level encapsulation techniques allow integration of software with various safety levels (QM to ASIL-D) from different sources, reducing the system complexity of implementing those safety levels.

The AURIX architecture offers the following features:

Hardware-focused safety concepts for reduced SW overhead
Lockstep with clock delay
Access permission system
Safety management unit
Safe DMA
I/O, clock and voltage monitors
Safety Software for checking the functionality of the core
ISO 26262 conformance to support safety requirements up to ASIL-D

Security Features

Infineon has integrated a programmable Hardware Security Module (HSM) into the AURIX family in line with EVITA (E-safety vehicle intrusion protected applications). This “embedded chipcard” protects against IP infringement, fraud and software hijacking.

Hardware Security Module (HSM)
Secure software updates, Secure Boot, Secure Key Update, Secure Communication
Immobilizer
Tuning protection
Mileage protection
Component protection
IP protection

Scalability

From Single Core to Triple Lockstep Core
80–300 MHz
256KB – 8MB Flash
48KB – 2.7MB SRAM
ASIL Level from QM up to ASIL D
HOT Package Option

Connectivity

Ethernet 100Mbit
FlexRay
High-Speed Serial Link IF
SPI, CAN (FD), LIN, UART
Hardware SENT interface for low CPU load
Camera Interface (up to 16-bit)
External ADC IF (up to 16-bit)
External Bus Interface for Memory Extension

Supply security

Infineon has set up dual-fab manufacturing using two local separated Frontend production sites. Both sites are using identical certified processes and tooling. All products from both sides will be AEC-Q100 qualified and are manufactured in a 65 nm technology.Infineon has officially stated that the embedded flash technology for TC39xXX utilizes a 40 nm manufacturing process.^[5]

Applications

Technical features