Top Qs
Timeline
Chat
Perspective
List of Intel graphics processing units
From Wikipedia, the free encyclopedia
Remove ads
This article contains information about Intel's GPUs (see Intel Graphics Technology) and motherboard graphics chipsets in table form. In 1982, Intel licensed the NEC μPD7220 and announced it as the Intel 82720 Graphics Display Controller.[1][2]
![]() | This article has multiple issues. Please help improve it or discuss these issues on the talk page. (Learn how and when to remove these messages)
|

Remove ads
Gen1
Intel's first generation GPUs:
Remove ads
Gen2
Intel marketed its second generation using the brand Extreme Graphics. These chips added support for texture combiners allowing support for OpenGL 1.3.
Remove ads
Gen3
Intel's first DirectX 9 GPUs with hardware Pixel Shader 2.0 support.
Gen4
The last generation of motherboard integrated graphics. Full hardware DirectX 10 support starting with GMA X3500.
- Each EU has a 128-bit wide FPU that natively executes four 32-bit operations per clock cycle.
Remove ads
Gen5
- Integrated graphics chip moved from motherboard into the processor.
- Improved gaming performance
- Can access CPU's cache
- Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle.[20]
- Hierarchical-Z compression and fast Z clear[21]
Remove ads
Gen6
- Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle.[20]
- Double peak performance per clock cycle compared to previous generation due to fused multiply-add instruction.[20]
- The entire GPU shares a sampler and an ROP.[20]
Remove ads
Gen7
- 1 FP32 ALUs : EUs : Subslices
- Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
- Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.
Remove ads
Gen7.5
- 1 FP32 ALUs : EUs : Subslices
- Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
- Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.
Remove ads
Gen8
- 1 FP32 ALUs : EUs : Subslices
- Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions is one per 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
- Each Subslice contains 8 EUs and a sampler (4 tex/clk[47]), and has 64 KB shared memory.
- Intel Quick Sync Video
- For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.
Remove ads
Gen9
Summarize
Perspective
- 1 FP32 ALUs : EUs : Subslices
- Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter (eighth in Apollo Lake) of the FP32 FLOPS.
- Each Subslice contains 8 EUs (two of which are disabled in GT1) and a sampler (4 tex/clk), and has 64 KB shared memory.
- Intel Quick Sync Video
- For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.
- WDDM 2.2 support with Windows Mixed Reality begins with KabyLake-based GPUs.[54]
Remove ads
Gen11
- 1 FP32 ALUs : EUs : Subslices
- Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
- Each Subslice contains 8 EUs and a sampler (4 tex/clk), and has 64 KB shared memory.
- Intel Quick Sync Video
- For Windows 10, the total system memory that is available for graphics use is half the system memory.
- No eDRAM.
Remove ads
Gen12
Summarize
Perspective
Intel Xe is a GPGPU and dGPU product line first released in 2020, in the mobile Tiger Lake line and Rocket Lake line.
- 1 FP32 ALUs: EUs: Subslices
Gen12.2
Summarize
Perspective
Intel Xe is a GPGPU and dGPU product line first released in 2021, in Alder Lake and Raptor Lake line.
Gen 12.5
- shading cores (ALU):texture mapping units (TMU):render output units (ROP):ray tracing units:tensor cores (XMX):execution Units
- Boost values (if available) are stated below the base value in italic.
- Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
- Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
Gen 12.7
Desktop
Mobile
- Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units
(tensor cores (XMX): execution units: render slices) - Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
- Boost values (if available) are stated below the base value in italic.
- Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
Workstation
- Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units
(tensor cores (XMX): execution Units: render slices) - Boost values (if available) are stated below the base value in italic.
- Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
- Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
Battlemage based
Summarize
Perspective
Desktop
- Pixel fillrate is calculated as the number of render output units (ROPs) multiplied by the base (or boost) core clock speed.
- Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
- Xe2-HPG Cores (Xe Vector Engines)
Unified Shaders : Texture Mapping Units : Render Output Units : Ray Tracing Cores : XMX Cores - Boost values (if available) are stated below the base value in italics.
Workstation
- Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
- Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
- Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units
(tensor cores (XMX): execution Units: render slices) - Boost values (if available) are stated below the base value in italic.
PowerVR based
Summarize
Perspective
See also
Notes
- Acronyms
- The following acronyms are used throughout the article.
- EU: Execution Unit
- iDCT: Inverse discrete cosine transform
- iMDCT: Inverse modified discrete cosine transform
- LF: In-loop deblocking filter
- MC: Motion compensation
- VLD: Variable-length code (sometimes referred to as slice-level acceleration)
- WMV9: Windows Media Video 9 codec
- Full hardware acceleration techniques
- Intel graphic processing units employ the following techniques in hardware acceleration of digital video playback.
References
Wikiwand - on
Seamless Wikipedia browsing. On steroids.
Remove ads