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International Symposium on Microarchitecture
From Wikipedia, the free encyclopedia
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The IEEE/ACM International Symposium on Microarchitecture® (MICRO) is an annual academic conference on microarchitecture, generally viewed as the top-tier academic conference on computer architecture.[1] It is not to be confused with a micro-conference. Particularly within the domains of microarchitecture and Code generation (compiler), MICRO is unrivaled and esteemed as the premier forum. Association for Computing Machinery's Special Interest Group on Microarchitecture (ACM SIGMICRO) and Institute of Electrical and Electronics Engineers Computer Society are technical sponsors.
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Events
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MICRO Test of Time (ToT) Award
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Perspective
The SIGMICRO Test of Time (ToT) Award recognizes influential papers from prior editions of the International Symposium on Microarchitecture (MICRO). It was first awarded in 2014 (a special inaugural year recognizing 10 papers from 1968–1992) and has since been awarded annually, typically to papers published 18–22 years prior to the award year.[2][3]
- Recent and past recipients
- 2024 (for MICRO 2006): Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches — Moinuddin K. Qureshi; Yale N. Patt.[4][5]
- 2023 (for MICRO 2003): Orion: A Power-Performance Simulator for Interconnection Networks — Hang-Sheng Wang; Xinping Zhu; Li-Shiuan Peh; Sharad Malik.[6]
- 2022 (for MICRO 2003): A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor — Shubhendu S. Mukherjee; Christopher T. Weaver; Joel S. Emer; Steven K. Reinhardt; Todd M. Austin.[7]
- 2022 (for MICRO 2003): Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data — Canturk Isci; Margaret Martonosi.[7]
- 2021 (for MICRO 2003): Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation — Dan Ernst; Nam Sung Kim; Shidhartha Das; Sanjay Pant; Rajeev R. Rao; Toan Pham; Conrad H. Ziesler; David T. Blaauw; Todd M. Austin; Krisztián Flautner; Trevor N. Mudge.[2]
- 2021 (for MICRO 2003): Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction — Rakesh Kumar; Keith I. Farkas; Norman P. Jouppi; Parthasarathy Ranganathan; Dean M. Tullsen.[2][8]
- 2020 (for MICRO 2000): A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality — Zhao Zhang; Zhichun Zhu; Xiaodong Zhang.[9]
- 2020 (for MICRO 1999): Fetch Directed Instruction Prefetching — Glenn Reinman; Brad Calder; Todd M. Austin.[9]
- 2020 (for MICRO 1998): A Dynamic Multithreading Processor — Haitham Akkary; Michael A. Driscoll.[9]
- 2019 (for MICRO 2001): Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution — Ravi Rajwar; James R. Goodman.[2]
- 2019 (for MICRO 1999): Selective Cache Ways: On-Demand Cache Resource Allocation — David H. Albonesi.[2][10]
- 2018 (for MICRO 1999): DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design — Todd M. Austin.[11][12]
- 2018 (for MICRO 1996): Assigning Confidence to Conditional Branch Predictions — Erik Jacobsen; Eric Rotenberg; James E. Smith.[11][12]
- 2018 (for MICRO 1996): Efficient Path Profiling — Thomas Ball; James R. Larus.[11][12]
- 2017 (for MICRO 1996): Exceeding the Dataflow Limit Via Value Prediction — Mikko H. Lipasti; John Paul Shen.[2]
- 2016 (for MICRO 1994): Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops — B. Ramakrishna Rau.[13][14]
- 2015 (for MICRO 1996): Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching — Eric Rotenberg; Steve Bennett; James E. Smith.[2]
- 2014 (inaugural set of 10 papers from 1968–1992).[3][15]
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References
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