LVCMOS

Low voltage complementary metal oxide semiconductor (LVCMOS) is a low voltage class of CMOS technology digital integrated circuits.

Overview

To obtain better performance and lower costs, semiconductor manufacturers reduce the device geometries of integrated circuits. With each reduction the associated operating voltage must also be reduced in order to maintain the same basic operational characteristics of the transistors. As semiconductor technology has progressed, LVCMOS power supply voltage and interface standards for decreasing voltages have been defined by the Joint Electron Device Engineering Council (JEDEC) for digital logic levels lower than 5 volts.

Logic Volts	Tolerance Volts	Tolerance Percent	References and Notes
5.0 V	+/-0.5 V	+/-10.0%	TTL logic, not LVCMOS
3.3 V	+/-0.3 V	+/-9.09%	JESD8C.01[1]
2.5 V	+/-0.2 V	+/-8.00%	JESD8-5A.01[2] JESD80[3]
1.8 V	+/-0.15 V	+/-8.33%	JESD8-7A[4] JESD76[5]
1.5 V	+/-0.1 V	+/-8.33%	JESD8-11A.01[6] JESD76-3[7]
1.2 V	+/-0.1 V	+/-8.33%	JESD8-12A.01[8] JESD76-2[9]
1.0 V	+/-0.1 V	+/-8.33%	JESD8-14A.01[10]
0.9 V	+/-0.045 V	+/-5.00%
0.8 V	+/-0.04 V	+/-5.00%
0.7 V	+/-0.05 V	+/-7.14%