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List of x86 virtualization instructions
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Instruction set extensions that have been added to the x86 instruction set in order to support hardware virtualization. These extensions provide instructions for entering and leaving a virtualized execution context and for loading virtual-machine control structures (VMCSs), which hold the state of the guest and host, along with fields which control processor behavior within the virtual machine.
![]() | This article may be too technical for most readers to understand. (July 2024) |
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AMD-V instructions
- For the rAX argument to the
VMRUN
,VMLOAD
,VMSAVE
,INVLPGA
andPVALIDATE
instructions, the choice of AX/EAX/RAX depends on address-size, which can be overridden with the 67h prefix. - Support for AMD-V was added in stepping F of the AMD K8, and is not available on earlier steppings.
- The
VMRUN
instruction will load only a limited subset of CPU state -VMLOAD
should be run beforeVMRUN
to load additional state.
Similarly, #VMEXIT will store only a limited amount of guest state to the VMCB, andVMSAVE
is needed to store additional state.
For simple intercept conditions where the VMM doesn't need to make use of the state items handled byVMSAVE
/VMLOAD
, the VMM may improve performance by abstaining from performingVMSAVE
/VMLOAD
before re-entering the virtual machine withVMRUN
. VMGEXIT
is executed asVMMCALL
if not executed by a SEV-ES guest.
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Intel VT-x instructions
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Intel virtualization instructions. VT-x is also supported on some processors from VIA and Zhaoxin.
- Executing any of the VT-x VMM instructions while within the VM guest will cause a VMEXIT.
If VMX operation has not been entered throughVMXON
, then all of the VT-x instructions (exceptVMXON
) will cause #UD. - The m64 argument to
VMPTRLD
,VMPTRST
,VMCLEAR
andVMXON
is a 64-bit physical address. - The m64 argument to
VMXON
is the 64-bit physical address to a "VMXON region", which is a 4Kbyte region that must be 4 Kbyte aligned. This region may be used by the processor to support VMX operation in an implementation-dependent manner and should never be accessed by software until the processor has left VMX operation through theVMXOFF
instruction. In systems with more than one logical CPU, entering VMX operation on more than one CPU requires a separate "VMXON region" for each CPU. - The
VMCALL
instruction can be executed by the VMM as well – doing so will cause a special SMM VM exit. - The invalidation types available for the
reg
argument ofINVEPT
are: - The invalidation types available for the
reg
argument ofINVVPID
are: - The functions available for
VMFUNC
in the EAX register are: - The operations available for
SEAMOPS
in the RAX register are:Any unsupported value in RAX will cause a #GP(0) exception.
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References
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