MERSI protocol

The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4.^[1] The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I). The M, E, S and I states are the same as in the MESI protocol. The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system. Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state. In both the MESI and MERSI protocols, the transition from the E to M is silent.^[2]

For any given pair of caches, the permitted states of a given cache line are as follows:

	M	E	R	S	I
M	N	N	N	N	Y
E	N	N	N	N	Y
R	N	N	N	N	Y
S	N	N	N	Y	Y
I	Y	Y	Y	Y	Y