OR-AND-invert

OR-AND-invert gates, or OAI-gates, are logic gates comprising OR gates followed by a NAND gate. They can be efficiently implemented in logic families like CMOS and TTL. They are dual to AND-OR-invert gates.

Overview

OR-AND-invert gates implement the inverted product of sums. ${\displaystyle n}$ groups of ${\displaystyle m_{i}}$, ${\displaystyle m_{i}\geq 1,i=1\ldots n}$ input signals combined with OR, and the results then combined with NAND.

Examples

2-1 OAI-gate

Symbol for an 2-1 OAI-gate. The OR gate has the inputs A and B.

A 2-1-OAI gate realizes the following function:

${\displaystyle Y={\overline {(A\lor B)\land C}}}$

Truth table 2-1 OAI
Input A   B   C			Output Y
0	0	0	1
0	0	1	1
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	0

2-2 OAI gate

A 2-2-OAI gate realizes the following function:

Failed to parse (SVG (MathML can be enabled via browser plugin): Invalid response ("Math extension cannot connect to Restbase.") from server "http://localhost:6011/en.wikipedia.org/v1/":): {\displaystyle Y = \overline{(A \lor B) \land (C \lor D)} }

Truth table 2-2 OAI
INPUT A   B   C   D				OUTPUT Q
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	0
0	1	1	0	0
0	1	1	1	0
1	0	0	0	1
1	0	0	1	0
1	0	1	0	0
1	0	1	1	0
1	1	0	0	1
1	1	0	1	0
1	1	1	0	0
1	1	1	1	0

Realization

Implementation of a 3-1 OAI-gate in CMOS

OAI-gates can efficiently be implemented as complex gates. An example of a 3-1 OAI-gate is shown in the figure below.^[1]

Examples of use

One possibility of implementing an XOR gate is by using a 2-2-OAI-gate with non-inverted and inverted inputs. ^[2]

Implementation of an XOR gate using a 2-2-OAI gate