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OR-AND-invert

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OR-AND-invert gates, or OAI-gates, are logic gates comprising OR gates followed by a NAND gate. They can be efficiently implemented in logic families like CMOS and TTL. They are dual to AND-OR-invert gates.

Overview

OR-AND-invert gates implement the inverted product of sums. groups of , input signals combined with OR, and the results then combined with NAND.

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Examples

2-1 OAI-gate

Thumb
Symbol for an 2-1 OAI-gate. The OR gate has the inputs A and B.

A 2-1-OAI gate realizes the following function:

Truth table 2-1 OAI
Input
A   B   C
Output
Y
0001
0011
0101
0110
1001
1010
1101
1110

2-2 OAI gate

A 2-2-OAI gate realizes the following function:

Truth table 2-2 OAI
INPUT
A   B   C   D
OUTPUT
Q
00001
00011
00101
00111
01001
01010
01100
01110
10001
10010
10100
10110
11001
11010
11100
11110
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Realization

Thumb
Implementation of a 3-1 OAI-gate in CMOS

OAI-gates can efficiently be implemented as complex gates. An example of a 3-1 OAI-gate is shown in the figure below.[1]

Examples of use

One possibility of implementing an XOR gate is by using a 2-2-OAI-gate with non-inverted and inverted inputs. [2]

Thumb
Implementation of an XOR gate using a 2-2-OAI gate

References

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