Patrick Groeneveld

Patrick Groeneveld is a Dutch-American electrical engineer and educator known for his work in Electronic Design Automation (EDA). He has held senior technical leadership roles at several major EDA companies and currently serves as a Senior Fellow at AMD and as adjunct lecturer at Stanford University.^[1][2]

Education

Groeneveld received his M.Sc. and Ph.D. degrees in Electrical Engineering from Delft University of Technology. His academic work focused on digital circuit design and computer-aided design tools.

Career

After his Ph.D., Groeneveld was awarded a research fellowship at the Royal Netherlands Academy of Arts and Sciences from 1991 to 1995.

Magma design automation

In 1997, Groeneveld joined Magma Design Automation as Chief Technologist, where he was a key architect of the company's flagship "Blast Fusion" product.^[3] This platform was recognized for unifying timing and physical design, which helped establish Magma as a major force in the EDA industry.^[1][2]

Synopsys and Cadence

After Magma was acquired by Synopsys in 2012, Groeneveld joined the company as a Scientist. He worked on design optimization technologies, architected infrastructure for tools like the Fusion Compiler, and contributed to the data model for the IC Compiler II (ICC2). He also served as Chairman of the Synopsys Technical Roadmap Team, advising leadership on technology and acquisitions. He later worked for a year as a Distinguished Engineer at Cadence Design Systems.

Cerebras and AMD

From 2019 to 2023, Groeneveld worked at Cerebras Systems, where he focused on the design software to map and route neural networks onto the company's Wafer-Scale Engine (WSE), a massive chip designed to accelerate AI training.^[3] In March 2024, he became a Senior Fellow at AMD.

Professional service and academia

Academic roles

Groeneveld was a full professor of Electrical Engineering at the Eindhoven University of Technology from 2002 to 2005.^[4] He currently teaches at Stanford University as an adjunct lecturer in the Electrical Engineering department, where he covers topics in VLSI design and EDA.^[5]

Community involvement and recognition

Groeneveld is closely involved with the Design Automation Conference (DAC), where he has been a member of the Executive Committee since 2008, serving as finance chair, and was the General Chair for the 49th DAC in 2012.^[6] He has also held leadership positions at the IEEE Council on Electronic Design Automation (CEDA), serving as Vice President of Publicity from 2014 to 2015.^[7] In 2013, he received an Outstanding Service Recognition from IEEE CEDA for his contributions.^[7]

Contributions

Groeneveld has been active in the academic and professional EDA community, organizing workshops, serving on program committees, and mentoring early-career researchers. He is closely involved with the Design Automation Conference (DAC), including the DAC Young Fellows program.

Research and patents

Groeneveld has authored numerous technical papers on topics including routing, congestion prediction, and physical design. His 2004 paper, "Probabilistic congestion prediction," is among his most cited works.^[8] He is an inventor on several patents, including:

• Method of designing a constraint-driven integrated circuit layout (US Patent 6,230,304)^[9]
• Method for storing multiple levels of design data in a common database (US Patent 6,505,328)^[10]

External links

• LinkedIn profile