Process–architecture–optimization model

Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.^[1]^[2]^[3]^[4]^[5]

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More information Wave, Process (die shrink) ...

Wave^[6]	Process (die shrink)	Architecture	Optimizations				Optional backport^[7]^[8]
1: 14 nm	2014: Broadwell (5th gen)	2015: Skylake (6th gen)	2016: Kaby Lake (7th gen)	2017: Coffee Lake (8th gen)	2018: Coffee Lake Refresh (9th gen)	2019: Comet Lake (10th gen)	2021: Rocket Lake (11th gen, Cypress Cove)
1: 14 nm	References:^[1]^[3]^[6]^[9]
2: 10 nm (Intel 7)	2018:^{[note 1]} Cannon Lake (8th gen, Palm Cove)	2019: Ice Lake (10th gen, Sunny Cove)	2020: Tiger Lake (11th gen, Willow Cove)	2021: Alder Lake (12th gen, Golden Cove)	2022: Raptor Lake (13th gen)	2023: Raptor Lake (14th gen)
2: 10 nm (Intel 7)	References:^[1]^[10]^[9]^[11]^[12]
3: Intel 4	2023: Meteor Lake (14th gen)
3: Intel 4	References:^[13]
3: Intel 20A and Intel 18A	2024: Arrow Lake (15th gen)	2024: Lunar Lake (16th gen)
3: Intel 20A and Intel 18A	References ^[14]

Process–architecture–optimization model

Roadmap

See also

Notes

References

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