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RISC-V assembly language
Assembly languages for the RISC-V computer architecture From Wikipedia, the free encyclopedia
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RISC-V assembly language is a low-level programming language that is used to produce object code for the RISC-V class of processors. Assembly languages are closely tied to the architecture's machine code instructions, allowing for precise control over hardware.
Assemblers include GNU Assembler and LLVM.
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Keywords
Reserved keywords of RISC-V assembly language.
- add
- addi
- and
- andi
- beq
- bge
- bgeu
- blt
- bltu
- bne
- lb
- lbu
- lh
- lhu
- lw
- or
- ori
- sb
- sh
- sll
- slli
- slt
- slti
- sltiu
- sltu
- sra
- srai
- srl
- srli
- sub
- sw
- xor
- xori
Mnemonics and opcodes
Each instruction in the RISC-V assembly language is represented by a mnemonic which often combines with one or more operands to translate into one or more bytes known as an opcode.
Registers
RISC-V processors feature a set of registers that serve as storage for binary data and addresses during program execution. These registers are categorized into integer registers and floating-point registers.
Instruction types
RISC-V instructions use variable-length encoding.
Extensions:
- atomic instructions
- single-precision floating-point
- double-precision floating-point
- bit manipulation
- cryptography
- hypervisor
- supervisor
- packed-SIMD instructions
- vector
Floating-point instructions
RISC-V assembly language includes instructions for a floating-point unit (FPU).
SIMD instructions
These largely perform the same operation in parallel on many values.
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Program flow
The RISC-V assembly has conditional branch instructions based on comparison: beq
(equal), bne
(not equal), blt
(less than, signed), bltu
(less than, unsigned), bge
(greater than or equal, signed), and bgeu
(greater than or equal, unsigned).
Examples
.section .text
.globl _start
_start:
lui a1, %hi(msg) # load msg(hi)
addi a1, a1, %lo(msg) # load msg(lo)
jalr ra, puts
2: j 2b
.section .rodata
msg:
.string "Hello World\n"
See also
External links
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