RISC-V instruction listings

List of RISC-V microprocessor instructions From Wikipedia, the free encyclopedia

The RISC-V instruction set refers to the set of instructions that RISC-V compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

RISC-V Integer Instructions

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The table below contains a list of the RV Integer Instructions.[1] The integer instruction set is divided in the base I part of the ISA that comes in a 32 bit RV32 and 64 bit RV64 version and M, B and Zicond extensions. There is also an A extension for atomic instructions and F and D instructions for floating point operations.

More information Instruction, Name ...
RV Integer (pseudo) Instructions
InstructionNameFormatExtensionRV64
lbLoad Byterd, imm12(rs)I
lhLoad Halfrd, imm12(rs)I
lwLoad Wordrd, imm12(rs)I
ldLoad Doublerd, imm12(rs)Ix
lbuLoad Byte (U)rd, imm12(rs)I
lhuLoad Half (U)rd, imm12(rs)I
lwuLoad Word (U)rd, imm12(rs)Ix
sbStore Byters1, imm12(rs2)I
shStore Halfrs1, imm12(rs2)I
swStore Wordrs1, imm12(rs2)I
sdStore Doublers1, imm12(rs2)Ix
liLoad Immediaterd, immI[note 1]
luiLoad Upper Immediaterd, imm20I
auipcAdd Upper Immediate to Program Counterrd, imm20I
mvMoVerd, rsI[note 2]
sext.bmove Sign EXTended least significant Byterd, rsB
sext.hmove Sign Extended least significant Halfrd, rsB
sext.wmove Sign EXTended least significant Wordrd, rsI[note 2]x
zext.bmove Zero EXTended least significant Byterd, rsI[note 2]
zext.hmove Zero EXTended least significant Halfrd, rsB
zext.wmove Zero EXTended least significant Wordrd, rsB[note 2]x
rev8move with REVersed byte orderrd, rsB
czero.eqzmove Conditional on EQual to Zero or ZEROrd, rs1, rs2Zicond
czero.nezmove Conditional on Not Equal to Zero or ZEROrd, rs1, rs2Zicond
addiADD Immediaterd, rs, imm12I
addADDrd, rs1, rs2I
sh1addSHift1 ADDrd, rs1, rs2B
sh2addSHift2 ADDrd, rs1, rs2B
sh3addSHift3 ADDrd, rs1, rs2B
add.wuADD Word(U to double)rd, rs1, rs2Bx
sh1add.wuSHift1 Word(U in double) Add to doublerd, rs1, rs2Bx
sh2add.wuSHift2 Word(U in double) Add to doublerd, rs1, rs2Bx
sh3add.wuSHift3 Word(U in double) Add to doublerd, rs1, rs2Bx
addiwADD Word to Word Immediaterd, rs, imm12Ix
addwADD Wordrd, rs1, rs2Ix
subSUBtractrd, rs1, rs2I
subwSUBtract Wordrd, rs1, rs2Ix
negNEGative.rd, rsI[note 2]
negwNegative Wordrd, rsI[note 2]x
mulMULtiplyrd, rs1, rs2M
mulwMULtiply Wordrd, rs1, rs2Mx
mulhMULtiply High partrd, rs1, rs2M
mulhuMULtiply High Part Unsignedrd, rs1, rs2M
mulhsuMULtiply High Part Unsigned Signedrd, rs1, rs2M
divDIViderd, rs1, rs2M
divuDIVide (U)rd, rs1, rs2M
remREMainderrd, rs1, rs2M
remuREMainder (U)rd, rs1, rs2M
minMINimumrd, rs1, rs2B
maxMAXimumrd, rs1, rs2B
minuMINimum (U)rd, rs1, rs2B
maxuMAXimum (U)rd, rs1, rs2B
seqzSet EQual to Zerord, rsI[note 2]
snezSet Not Equal to Zerord, rsI[note 2]
sltiSet Less Than Immediaterd, rs, imm12I
sltSet Less Thanrd, rs1, rs2I
sltiuSet Less Than Immediate (U)rd, rs, imm12I
sltuSet Less Than (U)rd, rs1, rs2I
bextiBit Extract Immediaterd, rs, imm5/6B
bextBit Extractrd, rs1, rs2B
andiAND Immediaterd, rs, imm12I
andANDrd, rs1, rs2I
andnAND Notrd, rs1, rs2B
bclriBit CLeaR Immediaterd, rs, imm5/6B
bclrBit CLeaRrd, rs1, rs2B
oriOR Immediaterd, rs, imm12I
orORrd, rs1, rs2I
ornOR Notrd, rs1, rs2B
bsetiBit SET Immediaterd, rs, imm5/6B
bsetBit SETrd, rs1, rs2B
xorieXclusive OR Immediaterd, rs, imm12I
xoreXclusive ORrd, rs1, rs2I
xnorNot XORrd, rs1, rs2B
binviBit INVert Immediaterd, rs, imm5/6B
binvBit INVertrd, rs1, rs2B
notNOTrd, rsI[note 2]
orc.bOR Combine within Bytesrd, rsB
slliShift Left Logical Immediaterd, rs, imm5/6I
sllShift Left Logicalrd, rs1, rs2I
slliwShift Left Logical Word Immediaterd, rs, imm5Ix
sllwShift Left Logical Wordrd, rs1, rs2Ix
slli.wuShift Left Logical Word (U in double) Immediaterd, rs, imm5/6Ix
srliShift Right Logical Immediaterd, rs, imm5/6I
srlShift Right Logicalrd, rs1, rs2I
srliwShift Right Logical Word Immediaterd, rs, imm5Ix
srlwShift Right Logical Wordrd, rs1, rs2Ix
sraiShift Left Arith Immediaterd, rs, imm5/6I
sraShift Right Arithmeticrd, rs1, rs2I
sraiwShift Left Arith Word Immediaterd, rs, imm5Ix
srawShift Right Arithmetic Wordrd, rs1, rs2Ix
roriROtate Right Immediaterd, rs, imm5/6B
rorROtate Rightrd, rs1, rs2B
rolROtate Leftrd, rs1, rs2B
roriwROtate Right Immediate Wordrd, rs, imm5Bx
rorwROtate Right Wordrd, rs1, rs2Bx
rolwROtate Left Wordrd, rs1, rs2Bx
clzCount Leading Zerosrd, rsB
clzwCount Leading Zeros in Wordrd, rsBx
ctzCount Trailing Zerosrd, rsB
ctzwCount Trailing Zeros in Wordrd, rsBx
cpopCount POPulation of 1srd, rsB
cpopwCount POPulation of 1s in Wordrd, rsBx
jJumplabelI[note 2]
jalJump And Linkrd, imm20I
jrJump Registerrs [, imm12]I[note 2]
jalrJump And Link Registerrd rs [, imm12]I
callCALLsymbolI[note 3]
tailTAIL callsymbolI[note 4]
retRETurn-
beqBranch ==rs1, rs2, labelI
bneBranch !=rs1, rs2, labelI
bltBranch <rs1, rs2, labelI
bgtBranch >rs1, rs2, labelI[note 2]
bgeBranch >=rs1, rs2, labelI
bleBranch <=rs1, rs2, labelI[note 2]
bltuBranch < (U)rs1, rs2, labelI
bgtuBranch > (U)rs1, rs2, labelI[note 2]
bgeuBranch >= (U)rs1, rs2, labelI
bleuBranch <= (U)rs1, rs2, labelI[note 2]
nopNoOPeration-I
ecallEnvironment CALL-I
ebreakEnvironment BREAK-I
Close

Remarks

  1. Assembler macro, for immediates needing less than 12 bit expands to addi rd zero imm
  2. Pseudo Instruction. Expands to single instruction.
  3. Assembler macro clobbering ra. Interacts with the loader symbol relocation. Expands to jal ra, imm or auipc ra, imm; jalr ra, ra imm combination
  4. Assembler macro, may clobber t1. Interacts with the loader symbol relocation. Expands to jal zero imm or auipc t1, imm; jalr zero t1, imm combination
  5. Pseudo instruction clobbering ra. Expands to jal zero, ra, 0

See also

References

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