Superlog HDL

Superlog HDL is a hardware description language (HDL) developed by Co-Design Automation, Inc. in the late 1990s.^[1] It was designed as an extension to Verilog with additional features for modeling complex hardware systems and supporting advanced formal verification functionality. Superlog played a significant role in the eventual development of SystemVerilog, which was standardized by Accellera and later adopted by the IEEE.^[2]

History

Co-Design Automation was a small California based private company^[1] co-founded by Simon Davidmann and Peter Flake, and backed by industry experts such as Andy Bechtolsheim co-founder of Sun Microsystems and Rajeev Madhavan founder of Magma Design Automation. Flake and Davidmann had both been involved with the development of HILO which had laid the foundations for Verilog.^[3]

Co-Design Automation introduced Superlog to address limitations in traditional Verilog for large-scale hardware projects. By combining hardware modeling constructs with higher-level verification features, Superlog aimed to provide a unified language for both design and testbench development.^[4]

In the early 2000s, Co-Design Automation collaborated with several semiconductor and EDA tool vendors to integrate Superlog capabilities into existing toolchains. This integration and growing interest in unified design/verification methodologies contributed to Accellera’s interest in incorporating Superlog concepts into a next-generation standard, which led to the formation of SystemVerilog.^[5]

The simulators for Superlog were developed by James Kenney and Phil Moorby.^[2] Phil Moorby was the initial creator of the Verilog HDL and the implementer of the original Verilog-XL simulator in Gateway Design/Cadence Design.^[6]

Co-Design was acquired by Synopsys in 2002 for $36M.^[7][8]

Language features

According to publications on the topic, Superlog included several enhancements over traditional Verilog:

• Object-oriented concepts for testbench structuring (classes, methods, etc.).^[9]
• Enhanced data types for modeling complex systems and transactions.^[10]
• Assertions for improved verification capabilities, foreshadowing SystemVerilog Assertions (SVA).^[11]
• Higher-level constructs enabling more concise and maintainable hardware verification code.^[10]

Many of these features influenced the eventual SystemVerilog standard, which combined Verilog HDL with Superlog-like constructs for a robust hardware description and verification language.^[12]

A book on SystemVerilog for Design^[11] by Davidmann, Flake, and Sutherland was published in 2003 including examples, language details and a discussion on the language development process and history. The ACM SIGPLAN (Special Interest Group on Programming Languages) HOPL (History of Programming Languages) conference invited a paper on the evolution of Verilog which includes examples and descriptions of Superlog constructs and how it evolved into SystemVerilog.^[2]

Adoption

Superlog, while never as widely adopted as Verilog or VHDL, gained recognition in certain circles of the semiconductor industry:

• Some early adopters included small processor design firms seeking integrated design-and-verification environments.^[7]
• Academic research projects in electronic design automation sometimes referenced Superlog as a potential successor or alternative to Verilog.^[13]

As SystemVerilog emerged and gained backing by major EDA vendors, Superlog’s direct use began to diminish, with most of its innovations folded into the newer standard.^[11]

Reception

Trade publications and electronics industry journalists described Superlog as an “ambitious” extension of Verilog, noting that it attempted to unify design and verification in a single language.^[4] Critics pointed out the lack of broad ecosystem support in the early stages and cautioned that industry inertia favored the established Verilog and VHDL standards.^[8]

Nevertheless, several commentators recognized that Superlog’s concepts significantly shaped the direction of SystemVerilog, which now stands as one of the primary standards for hardware description and verification.^[7]

Legacy and influence

Superlog’s primary legacy is its direct influence on SystemVerilog, which was standardized by Accellera in 2002 and later became IEEE 1800.^[14] This standard has been widely adopted for digital system and integrated circuit design. Many of the object-oriented and assertion-based verification features originally showcased in Superlog are now foundational in SystemVerilog testbench methodologies.^[2][11][7]

See also

• Hardware description language
• Hardware verification language
• SystemVerilog
• Verilog
• VHDL