<span class="mw-page-title-main">Sandy Bridge</span>

Sandy Bridge

<p><b>Sandy Bridge</b> is the <a href="/en/List_of_Intel_codenames" title="List of Intel codenames" class="wl">codename</a> for Intel's <a href="/en/32_nm_process" title="32 nm process" class="wl">32 nm</a> <a href="/en/Microarchitecture" title="Microarchitecture" class="wl">microarchitecture</a> used in the second generation of the <a href="/en/Intel_Core" title="Intel Core" class="wl">Intel Core processors</a> (<a href="/en/Intel_Core_i7" title="Intel Core i7" class="mw-redirect wl">Core i7</a>, <a href="/en/Intel_Core_i5" title="Intel Core i5" class="mw-redirect wl">i5</a>, <a href="/en/Intel_Core_i3" title="Intel Core i3" class="mw-redirect wl">i3</a>). The Sandy Bridge microarchitecture is the successor to <a href="/en/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)" class="wl">Nehalem</a> and <a href="/en/Westmere_(microarchitecture)" title="Westmere (microarchitecture)" class="wl">Westmere microarchitecture</a>. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the <a href="/en/Intel_Core#Sandy_Bridge_microarchitecture_based" title="Intel Core" class="wl">Core</a> brand.<span class="mw-ref reference" id="cite_ref-man_2-0"><a href="#cite_note-man-2" style="counter-reset: mw-Ref 2;"><span class="mw-reflink-text">[2]</span></a></span><span class="mw-ref reference" id="cite_ref-3"><a href="#cite_note-3" style="counter-reset: mw-Ref 3;"><span class="mw-reflink-text">[3]</span></a></span></p>

<div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none" about="#mwt1">Intel processor microarchitecture</div>
<style data-mw-deduplicate="TemplateStyles:r1066479718" typeof="mw:Extension/templatestyles mw:Transclusion">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}body.skin-minerva .mw-parser-output .infobox-header,body.skin-minerva .mw-parser-output .infobox-subheader,body.skin-minerva .mw-parser-output .infobox-above,body.skin-minerva .mw-parser-output .infobox-title,body.skin-minerva .mw-parser-output .infobox-image,body.skin-minerva .mw-parser-output .infobox-full-data,body.skin-minerva .mw-parser-output .infobox-below{text-align:center}</style><div class='mobile-collapse'><header class="mobile-collapse-header mobile-collapse-btn"><b>Quick facts: General information, Launched, Discontinued, ...</b> <span class='arrow'>▼</span></header> <table class="infobox mobile-collapse-element"><caption class="infobox-title">Sandy Bridge</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">January 9, 2011<span class="noprint"><span>;</span><span> </span>12 years ago</span><span style="display:none"><span>&nbsp;</span>(<span class="bday dtstart published updated">January 9, 2011</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">September 27, 2013 <span class="mw-ref reference" id="cite_ref-1"><a href="#cite_note-1" style="counter-reset: mw-Ref 1;"><span class="mw-reflink-text">[1]</span></a></span></td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80619 (extreme desktop)<br>80620 (server LGA1356)<br>80621 (server LGA2011)<br>80623 (desktop)<br>80627 (mobile)</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/en/Central_processing_unit" title="Central processing unit" class="wl">CPU</a> <a href="/en/Clock_rate" title="Clock rate" class="wl">clock rate</a></th><td class="infobox-data">1.60<span>&nbsp;</span>GHz to 3.60<span>&nbsp;</span>GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/en/Direct_Media_Interface" title="Direct Media Interface" class="wl">DMI</a> speeds</th><td class="infobox-data">5.00<span>&nbsp;</span>GT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="/en/CPU_cache" title="CPU cache" class="wl">cache</a></th><td class="infobox-data">64<span>&nbsp;</span><a href="/en/Kibibyte" title="Kibibyte" class="mw-redirect wl">KB</a> per core</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">256<span>&nbsp;</span>KB per core</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">1<span>&nbsp;</span>MB to 8<span>&nbsp;</span>MB shared<br>10<span>&nbsp;</span>MB to 15<span>&nbsp;</span>MB (Extreme)<br>3<span>&nbsp;</span>MB to 20<span>&nbsp;</span>MB (Xeon)</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/en/Microarchitecture" title="Microarchitecture" class="wl">Microarchitecture</a></th><td class="infobox-data">Sandy Bridge</td></tr><tr><th scope="row" class="infobox-label"><a href="/en/Instruction_set_architecture" title="Instruction set architecture" class="wl">Instruction<span>&nbsp;</span>set</a></th><td class="infobox-data"><a href="/en/X86-64" title="X86-64" class="wl">x86-64</a></td></tr><tr><th scope="row" class="infobox-label">Instructions</th><td class="infobox-data"><a href="/en/X86" title="X86" class="wl">x86</a>, <a href="/en/X86-64" title="X86-64" class="wl">x86-64</a></td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409" typeof="mw:Extension/templatestyles">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li><a href="/en/MMX_(instruction_set)" title="MMX (instruction set)" class="wl">MMX</a>, <a href="/en/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions" class="wl">SSE</a>, <a href="/en/SSE2" title="SSE2" class="wl">SSE2</a>, <a href="/en/SSE3" title="SSE3" class="wl">SSE3</a>, <a href="/en/SSSE3" title="SSSE3" class="wl">SSSE3</a>, <a href="/en/SSE4" title="SSE4" class="wl">SSE4</a>, <a href="/en/SSE4.1" title="SSE4.1" class="mw-redirect wl">SSE4.1</a>, <a href="/en/SSE4.2" title="SSE4.2" class="mw-redirect wl">SSE4.2</a>, <a href="/en/Advanced_Vector_Extensions" title="Advanced Vector Extensions" class="wl">AVX</a></li><li><a href="/en/Intel_VT-x" title="Intel VT-x" class="mw-redirect wl">VT-x</a>, <a href="/en/Intel_VT-d" title="Intel VT-d" class="mw-redirect wl">VT-d</a></li><li><a href="/en/AES_instruction_set" title="AES instruction set" class="wl">AES-NI</a>, <a href="/en/CLMUL_instruction_set" title="CLMUL instruction set" class="wl">CLMUL</a>, <a href="/en/Trusted_Execution_Technology" title="Trusted Execution Technology" class="wl">TXT</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/en/Transistor_count" title="Transistor count" class="wl">Transistors</a></th><td class="infobox-data"><div class="plainlist"><ul><li>504M to 2.27B <a href="/en/32_nanometer" title="32 nanometer" class="mw-redirect wl">32nm</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/en/Multi-core_processor" title="Multi-core processor" class="wl">Cores</a></th><td class="infobox-data"><div class="plainlist"><ul><li>1–4 (4-6 Extreme, 2-8 Xeon)</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/en/Graphics_processing_unit" title="Graphics processing unit" class="wl">GPU(s)</a></th><td class="infobox-data"><a href="/en/Intel_HD_Graphics" title="Intel HD Graphics" class="mw-redirect wl">HD Graphics</a><br>650<span>&nbsp;</span><a href="/en/Hertz" title="Hertz" class="wl">MHz</a> to 1100<span>&nbsp;</span>MHz<br><a href="/en/Intel_HD_Graphics" title="Intel HD Graphics" class="mw-redirect wl">HD Graphics 2000</a><br>650<span>&nbsp;</span><a href="/en/Hertz" title="Hertz" class="wl">MHz</a> to 1250<span>&nbsp;</span>MHz<br><a href="/en/Intel_HD_Graphics" title="Intel HD Graphics" class="mw-redirect wl">HD Graphics 3000</a><br>650<span>&nbsp;</span>MHz to 1350<span>&nbsp;</span>MHz<br><a href="/en/Intel_HD_Graphics" title="Intel HD Graphics" class="mw-redirect wl">HD Graphics P3000</a><br>850<span>&nbsp;</span>MHz to 1350<span>&nbsp;</span>MHz</td></tr><tr><th scope="row" class="infobox-label">Socket(s)</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="/en/LGA_1155" title="LGA 1155" class="wl">LGA 1155</a> (desktops and workstations)</li><li><a href="/en/LGA_2011" title="LGA 2011" class="wl">LGA 2011</a> (high-end servers)</li><li><a href="/en/LGA_1356" title="LGA 1356" class="wl">LGA 1356</a> (low-end, dual-processor servers)</li><li><a href="/en/Socket_G2" title="Socket G2" class="wl">Socket G2</a></li><li><span class="new">BGA-1023</span></li><li><span class="new">BGA-1224</span></li><li><span class="new">BGA-1284</span></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Model(s)</th><td class="infobox-data"><div class="plainlist"><ul><li>Celeron Series<br>Pentium Series<br>Core i3/i5/i7/i7 Extreme Series<br><a href="/en/Intel_Sandy_Bridge-based_Xeon_microprocessors" title="Intel Sandy Bridge-based Xeon microprocessors" class="wl">Xeon E3/E5 Series</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="/en/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)" class="wl">Nehalem</a> (Tock)<br><a href="/en/Westmere_(microarchitecture)" title="Westmere (microarchitecture)" class="wl">Westmere</a> (Tick)</td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data"><a href="/en/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)" class="wl">Ivy Bridge</a> (Tick)<br><a href="/en/Haswell_(microarchitecture)" title="Haswell (microarchitecture)" class="wl">Haswell</a> (Tock)</td></tr><tr><th colspan="2" class="infobox-header">Support status</th></tr><tr><td colspan="2" class="infobox-full-data">Unsupported</td></tr></tbody></table> <footer class='mobile-collapse-footer mobile-collapse-btn'><b>Close</b> <span class='arrow'>▲</span></footer></div>

<figure class="mw-default-size wiki-thumb"><a href="/en/File:Intel_CPU_Core_i7_2600K_Sandy_Bridge_perspective.jpg" class="mw-file-description image media-thumb" data-hash="File:Intel_CPU_Core_i7_2600K_Sandy_Bridge_perspective.jpg"><img loading="lazy" src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b3/Intel_CPU_Core_i7_2600K_Sandy_Bridge_perspective.jpg/220px-Intel_CPU_Core_i7_2600K_Sandy_Bridge_perspective.jpg" decoding="async" data-file-width="3685" data-file-height="2500" data-file-type="bitmap" height="149" width="220" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b3/Intel_CPU_Core_i7_2600K_Sandy_Bridge_perspective.jpg/330px-Intel_CPU_Core_i7_2600K_Sandy_Bridge_perspective.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b3/Intel_CPU_Core_i7_2600K_Sandy_Bridge_perspective.jpg/440px-Intel_CPU_Core_i7_2600K_Sandy_Bridge_perspective.jpg 2x" alt="Intel_CPU_Core_i7_2600K_Sandy_Bridge_perspective.jpg"></a><figcaption>Bottom view of a Sandy Bridge i7-2600k</figcaption></figure>
<figure class="mw-default-size wiki-thumb"><a href="/en/File:Intel_i5-2500.jpg" class="mw-file-description image media-thumb" data-hash="File:Intel_i5-2500.jpg"><img loading="lazy" src="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Intel_i5-2500.jpg/220px-Intel_i5-2500.jpg" decoding="async" data-file-width="4014" data-file-height="3898" data-file-type="bitmap" height="214" width="220" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Intel_i5-2500.jpg/330px-Intel_i5-2500.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/83/Intel_i5-2500.jpg/440px-Intel_i5-2500.jpg 2x" alt="Intel_i5-2500.jpg"></a><figcaption>Top of a Sandy Bridge i5</figcaption></figure>

<p>Sandy Bridge is manufactured in the <a href="/en/32_nanometer" title="32 nanometer" class="mw-redirect wl">32 nm</a> process and has a soldered contact with the die and IHS (Integrated Heat Spreader), while Intel's subsequent generation <a href="/en/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)" class="wl">Ivy Bridge</a> uses a <a href="/en/22_nanometer" title="22 nanometer" class="mw-redirect wl">22 nm</a> <a href="/en/Die_shrink" title="Die shrink" class="wl">die shrink</a> and a TIM (Thermal Interface Material) between the die and the IHS.</p>



Sandy Bridge is the codename for Intel's 32 nm microarchitecture used in the second generation of the Intel Core processors . The Sandy Bridge microarchitecture is the successor to Nehalem and Westmere microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand. Sandy Bridge is manufactured in the 32 nm process and has a soldered contact with the die and IHS , while Intel's subsequent generation Ivy Bridge uses a 22 nm die shrink and a TIM between the die and the IHS. 