REX prefix

The REX prefix (from "register extensions") and REX coding scheme was introduced as part of AMD's x86-64 instruction set architecture that extended Intel's IA-32 instruction set architecture for microprocessors from Intel, AMD and others.

It provides additional space for encoding 64-bit addressing modes and additional registers present in the x86-64 architecture.

The one-byte REX prefix can be added to new and existing instructions. It provides 4 bits of payload in total and allows addressing 16 registers.

A two-byte REX2 prefix was proposed by Intel's Advanced Performance Extensions in 2023 that would offer 8 bits of payload and allow addressing 32 registers.

Instruction encoding

Instruction format using the REX prefix

# of bytes		1, 2	1	1	0, 1	0, 1, 2, 4	0, 1
Part	[Prefixes]	[REX]	OPCODE	ModR/M	[SIB]	[DISP]	[IMM]

The REX coding scheme uses an opcode prefix consisting of one byte, which may be added to existing or new instruction codes.^[1]

It has the four high-order bits set to four, which replaces sixteen opcodes numbered 0x40–0x4F. Previously, those opcodes were individual INC and DEC instructions for the eight standard processor registers; x86-64 code must use ModR/M INC and DEC instructions.^[2]

In the x86 architecture, instructions with a memory operand almost always use the ModR/M byte which specifies the addressing mode. This byte has three bit fields:

• mod, bits [7:6] - combined with the r/m field, encodes either 8 registers or 24 addressing modes. Also encodes opcode information for some instructions.
• reg/opcode, bits [5:3] - depending on primary opcode byte, specifies either a register or three more bits of opcode information.
• r/m, bits [2:0] - can specify a register as an operand, or combine with the mod field to encode an addressing mode.

The base-plus-index and scale-plus-index forms of 32-bit addressing (encoded with r/m = 100 and mod ≠ 11) require another addressing byte, the SIB byte. It has the following fields:

• scale factor, encoded with bits [7:6]
• index register, bits [5:3]
• base register, bits [2:0].

REX encoding

Byte	Bit
REX
	7	6	5	4	3	2	1	0
0 (0x4_)	0	1	0	0	W	R	X	B
REX2 (2-byte REX)
	7	6	5	4	3	2	1	0
0 (0xD5)	1	1	0	1	0	1	0	1
1	M0	R4	X4	B4	W	R3	X3	B3

The REX prefix's bit-field W changes the operand size to 64 bits, R expands reg to 4 bits, B expands r/m (or opreg in the few opcodes that encode the register in the 3 lowest opcode bits, such as "POP reg"), and X and B expand index and base in the SIB byte.

The REX2 prefix is a 2-byte variant of the REX prefix, that is proposed with Intel's Advanced Performance Extensions and allows addressing 32 registers.

• R₃, X₃, and B₃ bits are the same as R, X and B bits in the REX prefix.
• R₄, X₄, and B₄ bits are additional bits used to encode the 32 EGPR registers.
• W bit is the same as in the REX prefix.
• M₀ bit selects between legacy map 0 (1-byte opcodes, no escape) and legacy map 1 (2-byte opcodes, escape 0x0F).

History

• In October 1999, AMD announces the AMD64 instruction set extension.^[3]
• In August 2000, AMD publishes the full specification.^[4]
• In April 2003, AMD releases the first processor with support for AMD64.
• In February 2004, Intel announces that it will implement the AMD64 instruction set extension for its processors.^[5][6]
• In June 2004, Intel releases its first processor with support for AMD64.
• In May 2008, Via releases its first processor with support for AMD64.
• In July 2023, Intel announces Advanced Performance Extensions (APX), introducing the REX2 prefix.

See also

• VEX prefix
• EVEX prefix