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Implementation of Transport Layer Security From Wikipedia, the free encyclopedia
wolfSSL is a small, portable, embedded SSL/TLS library targeted for use by embedded systems developers. It is an open source implementation of TLS (SSL 3.0, TLS 1.0, 1.1, 1.2, 1.3, and DTLS 1.0, 1.2, and 1.3) written in the C programming language. It includes SSL/TLS client libraries and an SSL/TLS server implementation as well as support for multiple APIs, including those defined by SSL and TLS. wolfSSL also includes an OpenSSL compatibility interface with the most commonly used OpenSSL functions.[4][5]
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Developer(s) | Todd Ouska |
---|---|
Initial release | February 19, 2006[1] |
Stable release | |
Repository | github |
Written in | C |
Operating system | Multi-platform |
Type | Cryptography library |
License | GPL-2.0-or-later or proprietary[3] |
Website | www |
wolfSSL is currently available for Microsoft Windows, Linux, macOS, Solaris, ESP32, ESP8266, Threadx, VxWorks, FreeBSD, NetBSD, OpenBSD, embedded Linux, Yocto Project, OpenEmbedded, WinCE, Haiku, OpenWrt, iPhone, Android, Wii, and GameCube through DevKitPro support, QNX, MontaVista, Tron variants, NonStop OS, OpenCL, Micrium's MicroC/OS-II, FreeRTOS, SafeRTOS, Freescale MQX, Nucleus, TinyOS, TI-RTOS, HP-UX, uTasker, uT-kernel, embOS, INtime, mbed, RIOT, CMSIS-RTOS, FROSTED, Green Hills INTEGRITY, Keil RTX, TOPPERS, PetaLinux, Apache Mynewt, and PikeOS.[6]
The genesis of wolfSSL dates to 2004. OpenSSL was available at the time, and was dual licensed under the OpenSSL License and the SSLeay license.[7] yaSSL, alternatively, was developed and dual-licensed under both a commercial license and the GPL.[8] yaSSL offered a more modern API, commercial style developer support and was complete with an OpenSSL compatibility layer.[4] The first major user of wolfSSL/CyaSSL/yaSSL was MySQL.[9] Through bundling with MySQL, yaSSL has achieved extremely high distribution volumes in the millions.
In February 2019, Daniel Stenberg, the creator of cURL, was hired by the wolfSSL project to work on cURL.[10]
The wolfSSL lightweight SSL library implements the following protocols:[11]
Protocol Notes:
wolfSSL uses the following cryptography libraries:
By default, wolfSSL uses the cryptographic services provided by wolfCrypt.[13] wolfCrypt Provides RSA, ECC, DSS, Diffie–Hellman, EDH, NTRU (deprecated and removed), DES, Triple DES, AES (CBC, CTR, CCM, GCM), Camellia, IDEA, ARC4, HC-128, ChaCha20, MD2, MD4, MD5, SHA-1, SHA-2, SHA-3, BLAKE2, RIPEMD-160, Poly1305, Random Number Generation, Large Integer support, base 16/64 encoding/decoding, and post-quantum cryptographic algorithms: ML-KEM (certified under FIPS 203) and ML-DSA (certified under FIPS 204).
wolfCrypt also includes support for the recent X25519 and Ed25519 algorithms.
wolfCrypt acts as a back-end crypto implementation for several popular software packages and libraries, including MIT Kerberos[14] (where it can be enabled using a build option).
CyaSSL+ includes NTRU[15] public key encryption. The addition of NTRU in CyaSSL+ was a result of the partnership between yaSSL and Security Innovation.[15] NTRU works well in mobile and embedded environments due to the reduced bit size needed to provide the same security as other public key systems. In addition, it's not known to be vulnerable to quantum attacks. Several cipher suites utilizing NTRU are available with CyaSSL+ including AES-256, RC4, and HC-128.
wolfSSL supports the following Secure Elements:
wolfSSL supports the following hardware technologies:
The following tables list wolfSSL's support for using various devices' hardware encryption with various algorithms.
Device | AES-GCM | AES-CCM | AES-CBC | AES-ECB | AES-CTR |
---|---|---|---|---|---|
Intel AES-NI
(Xeon and Core processor families) |
All | All | All | All | All |
Freescale
Cryptographic Accelerator and Assurance Module (CAAM) |
All | All | All | All | |
Freescale Coldfire SEC
(NXP MCF547X and MCF548X) |
All | ||||
Freescale Kinetis MMCAU
K50, K60, K70, and K80 (ARM Cortex-M4 core) |
All | All | All | All | |
STMicroelectronics STM32
F1, F2, F4, L1, W Series (ARM Cortex - M3/M4) |
All | All | |||
Cavium NITROX
(III/V PX processors) |
All | ||||
Microchip PIC32 MX/MZ
(Embedded Connectivity) |
All | All | All | ||
Texas Instruments TM4C1294
(ARM Cortex-M4F) |
All | All | All | All | All |
Nordic NRF51 Archived 2018-06-19 at the Wayback Machine
(Series SoC family, 32-bit ARM Cortex M0 processor core) |
128-bit | ||||
ARMv8 | All | All | All | ||
Intel QuickAssist Technology | All | All | |||
Freescale NXP LTC | All | All | All | All | All |
Xilinx Zynq UltraScale+ | 256-bit | ||||
Renesas RX65N (R5F565NEHDFB) | All | All | |||
Renesas RX72N (RTK5RX72N0C00000BJ) | All | All | |||
Renesas RX MPU (R5F571MLDDFC) | All | All | |||
Renesas Synergy DK-S7G2 | 128-bit |
- "All" denotes 128, 192, and 256-bit supported block sizes
Device | DES-CBC | DES-ECB | 3DES-CBC |
---|---|---|---|
Freescale Coldfire SEC
(NXP MCF547X and MCF548X) |
64 bit | 192 bit | |
Freescale Kinetis MMCAU
K50, K60, K70, and K80 (ARM Cortex-M4 core) |
64 bit | 192 bit | |
STMicroelectronics STM32
F1, F2, F4, L1, W Series (ARM Cortex - M3/M4) |
64 bit | 64 bit (encrypt) | 192 bit |
Cavium NITROX
(III/V PX processors) |
192 bit | ||
Microchip PIC32 MX/MZ
(Embedded Connectivity) |
64 bit | 192 bit | |
Texas Instruments TM4C1294
(ARM Cortex-M4F) |
64 bit | 192 bit |
Device | RC4 | ChaCha20 |
---|---|---|
AVX1/AVX2
(Intel and AMD x86) |
Supported | |
Cavium NITROX
(III/V PX processors) |
2048 bit max. |
Device | MD5 | SHA1 | SHA2 | SHA-256 | SHA-384 | SHA-512 |
---|---|---|---|---|---|---|
AVX1/AVX2
(Intel and AMD x86) |
Supported | Supported | Supported | |||
Freescale Kinetis MMCAU
K50, K60, K70, and K80 (ARM Cortex-M4 core) |
Supported | Supported | Supported | |||
STMicroelectronics STM32
F1, F2, F4, L1, W Series (ARM Cortex - M3/M4) |
Supported | Supported | ||||
Microchip PIC32 MX/MZ
(Embedded Connectivity) |
Supported | Supported | Supported | |||
ARMv8 | Supported | |||||
Intel QuickAssist Technology | Supported | Supported | Supported | |||
Freescale NXP LTC | Supported | Supported | ||||
Xilinx Zynq UltraScale+ | Supported | |||||
Renesas Synergy DK-S7G2 | Supported | Supported | ||||
Renesas RX65N (R5F565NEHDFB) | Supported | Supported | ||||
Renesas RX72N (RTK5RX72N0C00000BJ) | Supported | Supported | Supported | |||
Renesas RX MPU (R5F571MLDDFC) | Supported | Supported | Supported |
Device | RSA | ECC | ECC-DHE | X25519 | Ed25519 |
---|---|---|---|---|---|
Cavium NITROX
(III/V PX processors) |
512–4096 bit | NIST Prime
192, 224, 256, 384, 521 |
|||
Microchip/Atmel
ATECC508A (compatible with any MPU or MCU including: Atmel SMART and AVR MCUs) |
256 bit
(NIST-P256) |
||||
Intel QuickAssist Technology | 512–4096 bit | 128, 256 bit | |||
Freescale NXP LTC | 512 - 4096 bit | 128, 256 bit | 128, 256 bit | 256 bit | 256 bit |
Xilinx Zynq UltraScale+ | 2048–4096 bit |
Device | HMAC-MD5 | HMAC-SHA1 | HMAC-SHA2 | HMAC-SHA256 | SHA-3 | Poly1305 |
---|---|---|---|---|---|---|
AVX1/AVX2
(Intel and AMD x86) |
Supported | |||||
Cavium NITROX
(III/V PX processors) |
Supported | Supported | Supported | Supported | ||
Microchip PIC32 MX/MZ
(Embedded Connectivity) |
Supported | Supported | Supported | |||
Intel QuickAssist Technology | Supported | Supported | ||||
Renesas RX65N (R5F565NEHDFB) | Supported | Supported | ||||
Renesas RX72N (RTK5RX72N0C00000BJ) | ||||||
Renesas RX MPU (R5F571MLDDFC) | Supported | Supported | ||||
Renesas Synergy DK-S7G2 | Supported |
Device | RNG |
---|---|
STMicroelectronics STM32
F1, F2, F4, L1, W Series (ARM Cortex - M3/M4) |
Supported |
Cavium NITROX
(III/V PX processors) |
Supported |
Nordic NRF51 Archived 2018-06-19 at the Wayback Machine
(Series SoC family, 32-bit ARM Cortex M0 processor core) |
Supported |
wolfSSL supports the following certifications:
wolfSSL is dual licensed:
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