ARM architecture family

Family of RISC-based computer architectures / From Wikipedia, the free encyclopedia

ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured for various environments. Arm Ltd. develops the architectures and licenses them to other companies, who design their own products that implement one or more of those architectures, including system on a chip (SoC) and system on module (SOM) designs, that incorporate different components such as memory, interfaces, and radios. It also designs cores that implement these instruction set architectures and licenses these designs to many companies that incorporate those core designs into their own products.

Quick facts: Designer, Bits, Introduced, Design, Type...
Bits32-bit, 64-bit
Introduced1985; 37 years ago (1985)
BranchingCondition code, compare and branch
Quick facts: Introduced, Version, Encoding, Endianness, Ex...
ARM 64/32-bit
Introduced2011; 11 years ago (2011)
VersionARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A, ARMv8.5-A, ARMv8.6-A, ARMv8-R, ARMv9
EncodingAArch64/A64 and AArch32/A32 use 32-bit instructions, T32 (Thumb-2) uses mixed 16- and 32-bit instructions[1]
EndiannessBi (little as default)
ExtensionsSVE, SVE2, SME, AES, SHA, TME; All mandatory: Thumb-2, Neon, VFPv4-D16, VFPv4; obsolete: Jazelle
General purpose31 × 64-bit integer registers[1]
Floating point32 × 128-bit registers[1] for scalar 32- and 64-bit FP or SIMD FP or integer; or cryptography
Quick facts: Version, Encoding, Endianness, Extensions, Re...
ARM 32-bit (Cortex)
VersionARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M
Encoding32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions.
EndiannessBi (little as default)
ExtensionsThumb-2, Neon, Jazelle, AES, SHA, DSP, Saturated, FPv4-SP, FPv5, Helium
General purpose15 × 32-bit integer registers, including R14 (link register), but not R15 (PC)
Floating pointUp to 32 × 64-bit registers,[2] SIMD/floating-point (optional)
Quick facts: Version, Encoding, Endianness, Extensions, Re...
ARM 32-bit (legacy)
VersionARMv6, ARMv5, ARMv4T, ARMv3, ARMv2
Encoding32-bit, except Thumb extension uses mixed 16- and 32-bit instructions.
EndiannessBi (little as default) in ARMv3 and above
ExtensionsThumb, Jazelle
General purpose15 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older)
Floating pointNone

There have been several generations of the ARM design. The original ARM1 used a 32-bit internal structure but had a 26-bit address space that limited it to 64 MB of main memory. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A architecture added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.[3] Arm Ltd. has also released a series of additional instruction sets for different rules; the "Thumb" extension adds both 32- and 16-bit instructions for improved code density, while Jazelle added instructions for directly handling Java bytecode. More recent changes include the addition of simultaneous multithreading (SMT) for improved performance or fault tolerance.[4]

Due to their low costs, minimal power consumption, and lower heat generation than their competitors, ARM processors are desirable for light, portable, battery-powered devices, including smartphones, laptops and tablet computers, and other embedded systems.[5][6][7] However, ARM processors are also used for desktops and servers, including the world's fastest supercomputer (Fugaku) from 2020[8] to 2022. With over 230 billion ARM chips produced,[9][10][11] as of 2022, ARM is the most widely used family of instruction set architectures (ISA) and the ISAs produced in the largest quantity.[12][6][13][14][15] Currently, the widely used Cortex cores, older "classic" cores, and specialised SecurCore cores variants are available for each of these to include or exclude optional capabilities.