ARM architecture family
Family of RISC-based computer architectures / From Wikipedia, the free encyclopedia
ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of RISC instruction set architectures (ISAs) for computer processors. Arm Ltd. develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses cores that implement these ISAs.
 | |
| Designer | |
|---|---|
| Bits | 32-bit, 64-bit |
| Introduced | 1985; 38 years ago (1985) |
| Design | RISC |
| Type | Register-Register |
| Branching | Condition code, compare and branch |
| Open | Proprietary |
| Introduced | 2011; 12 years ago (2011) |
|---|---|
| Version | ARMv8-R, ARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A, ARMv8.5-A, ARMv8.6-A, ARMv8.7-A, ARMv8.8-A, ARMv8.9-A, ARMv9.0-A, ARMv9.1-A, ARMv9.2-A, ARMv9.3-A, ARMv9.4-A |
| Encoding | AArch64/A64 and AArch32/A32 use 32-bit instructions, T32 (Thumb-2) uses mixed 16- and 32-bit instructions[1] |
| Endianness | Bi (little as default) |
| Extensions | SVE, SVE2, SME, AES, SHA, TME; All mandatory: Thumb-2, Neon, VFPv4-D16, VFPv4; obsolete: Jazelle |
| Registers | |
| General-purpose | 31 × 64-bit integer registers[1] |
| Floating point | 32 × 128-bit registers[1] for scalar 32- and 64-bit FP or SIMD FP or integer; or cryptography |
| Version | ARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M |
|---|---|
| Encoding | 32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions. |
| Endianness | Bi (little as default) |
| Extensions | Thumb-2, Neon, Jazelle, AES, SHA, DSP, Saturated, FPv4-SP, FPv5, Helium |
| Registers | |
| General-purpose | 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC) |
| Floating point | Up to 32 × 64-bit registers,[2] SIMD/floating-point (optional) |
| Version | ARMv6, ARMv5, ARMv4T, ARMv3, ARMv2 |
|---|---|
| Encoding | 32-bit, except Thumb extension uses mixed 16- and 32-bit instructions. |
| Endianness | Bi (little as default) in ARMv3 and above |
| Extensions | Thumb, Jazelle |
| Registers | |
| General-purpose | 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older) |
| Floating point | None |
Due to their low costs, low power consumption, and low heat generation, ARM processors are useful for light, portable, battery-powered devices, including smartphones, laptops, and tablet computers, as well as embedded systems.[3][4][5] However, ARM processors are also used for desktops and servers, including the world's fastest supercomputer (Fugaku) from 2020[6] to 2022. With over 230 billion ARM chips produced,[7][8][9] as of 2022[update], ARM is the most widely used family of instruction set architectures.[10][4][11][12][13]
There have been several generations of the ARM design. The original ARM1 used a 32-bit internal structure but had a 26-bit address space that limited it to 64 MB of main memory. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A architecture added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.[14] Arm Ltd. has also released a series of additional instruction sets for different rules; the "Thumb" extension adds both 32- and 16-bit instructions for improved code density, while Jazelle added instructions for directly handling Java bytecode. More recent changes include the addition of simultaneous multithreading (SMT) for improved performance or fault tolerance.[15]
Oops something went wrong: