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Puma (microarchitecture)
Microarchitecture by AMD From Wikipedia, the free encyclopedia
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The Puma Family 16h is a low-power microarchitecture by AMD for its APUs. It succeeds the Jaguar as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The Beema line of processors are aimed at low-power notebooks, and Mullins are targeting the tablet sector.
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Design
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The Puma cores use the same microarchitecture as Jaguar, and inherits the design:
- Out-of-order execution and Speculative execution, up to 4 CPU cores
- Two-way integer execution
- Two-way 128-bit wide floating-point and packed integer execution
- Integer hardware divider
- Puma does not feature clustered multi-thread (CMT), meaning that there are no "modules"
- Puma does not feature Heterogeneous System Architecture or zero-copy[2]
- 32 KiB instruction + 32 KiB data L1 cache per core
- 1–2 MiB unified L2 cache shared by two or four cores
- Integrated single channel memory controller supporting 64bit DDR3L
- 3.1 mm2 area per core
Instruction set support
Like Jaguar, the Puma core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.[1]
Improvements over Jaguar
- 19% CPU core leakage reduction at 1.2V[3]
- 38% GPU leakage reduction
- 500 mW reduction in memory controller power
- 200 mW reduction in display interface power
- Chassis temperature aware turbo boost[4]
- Selective boosting according to application needs (intelligent boost)
- Support for ARM TrustZone via integrated Cortex-A5 processor
- Support for DDR3L-1866 memory[5]
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Puma+
AMD released a revision of the Puma microarchitecture, Puma+, which is integrated into the Carrizo-L APU platform.
Features
Processors
Desktop/Mobile (Beema)
Tablet (Mullins)
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References
External links
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