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List of AMD processors with 3D graphics
From Wikipedia, the free encyclopedia
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This is a list of microprocessors designed by AMD containing a 3D integrated graphics processing unit (iGPU), including those under the AMD APU (Accelerated Processing Unit) product series.
Features overview
The following table shows features of AMD's processors with 3D graphics, including APUs.
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
- To feed more than two displays, the additional panels must have native DisplayPort support.[10] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
- DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.
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Graphics API overview
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The following table shows the graphics and compute APIs support across ATI/AMD GPU microarchitectures. Note that a branding series might include older generation chips.
- Radeon 7000 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders.
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Desktop processors with 3D graphics
APU or Radeon Graphics branded
Lynx: "Llano" (2011)
- Socket FM1
- CPU: K10 (also Husky or K10.5) cores with an upgraded Stars architecture, no L3 cache
- GPU: TeraScale 2 (Evergreen); all A and E series models feature Redwood-class integrated graphics on die (BeaverCreek for the dual-core variants and WinterPark for the quad-core variants). Sempron and Athlon models exclude integrated graphics.[24]
- List of embedded GPU's
- Support for up to four DIMMs of up to DDR3-1866 memory
- Fabrication 32 nm on GlobalFoundries SOI process; Die size: 228 mm2, with 1.178 billion transistors[25][26]
- 5 GT/s UMI
- Integrated PCIe 2.0 controller
- Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
- Select models support Hybrid Graphics technology to assist a discrete Radeon HD 6450, 6570, or 6670 discrete graphics card. This is similar to the Hybrid CrossFireX technology available in the AMD 700 and 800 chipset series
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
- Models with "K" suffixes feature an unlocked multiplier and overclockable GPU.
Virgo: "Trinity" (2012)
- Fabrication 32 nm on GlobalFoundries SOI process
- Socket FM2
- CPU: Piledriver
- L1 Cache: 16 KB Data per core and 64 KB Instructions per module
- GPU TeraScale 3 (VLIW4)
- Die Size: 246 mm2, 1.303 Billion transistors[28]
- Support for up to four DIMMs of up to DDR3-1866 memory
- 5 GT/s UMI
- GPU (based on VLIW4 architecture) instruction support: DirectX 11, Opengl 4.2, DirectCompute, Pixel Shader 5.0, Blu-ray 3D, OpenCL 1.2, AMD Stream, UVD3
- Integrated PCIe 2.0 controller, and Turbo Core technology for faster CPU/GPU operation when the thermal specification permits
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, F16C,[29] ABM, BMI1, TBM
- Sempron and Athlon models exclude integrated graphics
- Select models support Hybrid Graphics technology to assist a Radeon HD 7350, 7450, 7470, 7550, 7570, 7670 discrete graphics card.[30][31] However, it has been found that this does not always improve 3D accelerated graphics performance.[32][33]
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Richland" (2013)
- Fabrication 32 nm on GlobalFoundries SOI process
- Socket FM2
- Two or four CPU cores based on the Piledriver microarchitecture
- GPU
- TeraScale 3 architecture
- HD Media Accelerator, AMD Hybrid Graphics
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Kabini" (2013, SoC)
- Fabrication 28 nm by GlobalFoundries
- Socket AM1, aka Socket FS1b (AM1 platform)
- 2 to 4 CPU Cores (Jaguar (microarchitecture))
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
- SoC with integrated memory, PCIe, 2× USB 3.0, 6× USB 2.0, Gigabit Ethernet, and 2× SATA III (6 Gb/s) controllers
- GPU based on Graphics Core Next (GCN)
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Kaveri" (2014) & "Godavari" (2015)
- Fabrication 28 nm by GlobalFoundries.
- Socket FM2+,[40] support for PCIe 3.0.
- Two or four CPU cores based on the Steamroller microarchitecture.
- Kaveri refresh models have codename Godavari.[41]
- Die Size: 245 mm2, 2.41 Billion transistors.[42]
- L1 Cache: 16 KB Data per core and 96 KB Instructions per module.
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
- Three to eight Compute Units (CUs) based on GCN 2nd gen microarchitecture;[43] 1 Compute Unit (CU) consists of 64 Unified Shader Processors : 4 Texture Mapping Units (TMUs) : 1 Render Output Unit (ROPs).
- Heterogeneous System Architecture-enabled zero-copy through pointer passing.
- SIP blocks: Unified Video Decoder, Video Coding Engine, TrueAudio.[44]
- Dual-channel (2× 64 Bit) DDR3 memory controller.
- Integrated custom ARM Cortex-A5 co-processor[45] with TrustZone Security Extensions[46] in select APU models, except the Performance APU models.[47]
- Select models support Hybrid Graphics technology by using a Radeon R7 240 or R7 250 discrete graphics card.[48]
- Display controller: AMD Eyefinity 2, 4K Ultra HD support, DisplayPort 1.2 Support.[49]
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Carrizo" (2016)
- Fabrication: 28 nm by GlobalFoundries
- Socket FM2+ or AM4, support for PCIe 3.0
- Two or four CPU cores based on the Excavator microarchitecture
- Die size: 250.04 mm2, 3.1 billion transistors[53]
- L1 cache: 32 KB data per core and 96 KB instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
- Single- or dual-channel DDR3 or DDR4 memory controller
- Third generation GCN-based GPU (Radeon M300)
- Integrated custom ARM Cortex-A5 coprocessor[45] with TrustZone security extensions[46][47]
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Bristol Ridge" (2016)
- Fabrication 28 nm by GlobalFoundries
- Socket AM4, support for PCIe 3.0
- Two or four "Excavator+" CPU cores
- L1 Cache: 32 KB Data per core and 96 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
- Dual-channel DDR4 memory controller
- PCI Express 3.0 x8 (No Bifurcation support, requires a PCI-e switch for any configuration other than x8)
- PCI Express 3.0 x4 as link to optional external chipset
- 4x USB 3.1 Gen 1
- Storage: 2x SATA and 2x NVMe or 2x PCI Express
- Third Generation GCN based GPU[56] with hybrid VP9 decoding
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Raven Ridge" (2018)
- Fabrication 14 nm by GlobalFoundries
- Transistors: 4.94 billion
- Die size: 210 mm²
- Socket AM4
- Zen CPU cores
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
- Dual-channel DDR4 memory controller
- Fifth generation GCN based GPU
- Video Core Next (VCN) 1.0
Common features of Zen based Raven Ridge desktop APUs:
- Socket: AM4.
- All the CPUs support DDR4-2666 (DDR4-2933 Ryzen) in dual-channel mode.
- L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
- L2 cache: 512 KB per core.
- All the CPUs support 16 PCIe 3.0 lanes.
- Includes integrated GCN 5th generation GPU.
- Fabrication process: GlobalFoundries 14LP.
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Picasso" (2019)
- Fabrication 12 nm by GlobalFoundries
- Transistors: 4.94 billion
- Die size: 210 mm²
- Socket AM4
- Zen+ CPU cores
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
- Dual-channel DDR4 memory controller
- Fifth generation GCN based GPU
- Video Core Next (VCN) 1.0
Common features of Zen+ based desktop APUs:
- Socket: AM4.
- All the CPUs support DDR4-2933 in dual-channel mode, while Athlon Pro 300GE and Athlon Silver Pro 3125GE support only DDR4-2666.
- L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
- L2 cache: 512 KB per core.
- All the CPUs support 16 PCIe 3.0 lanes.
- Includes integrated GCN 5th generation GPU.
- Fabrication process: GlobalFoundries 12LP.
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Renoir" (2020)
- Fabrication 7 nm by TSMC
- Socket AM4
- Up to eight Zen 2 CPU cores
- Dual-channel DDR4 memory controller
Common features of Ryzen 4000 desktop APUs:
- Socket: AM4.
- All the CPUs support DDR4-3200 in dual-channel mode.
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 512 KB per core.
- All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
- Includes integrated GCN 5th generation GPU.
- Fabrication process: TSMC 7FF.
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Cezanne" (2021)
- Fabrication 7 nm by TSMC
- Socket AM4
- Up to eight Zen 3 CPU cores
- Dual-channel DDR4 memory controller
Common features of Ryzen 5000 desktop APUs:
- Socket: AM4.
- All the CPUs support DDR4-3200 in dual-channel mode.
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 512 KB per core.
- All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
- Includes integrated GCN 5th generation GPU.
- Fabrication process: TSMC 7FF.
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
Non APU or Radeon Graphics branded
"Raphael" (2022)
- Fabrication 5 nm (CCD) and 6 nm (cIOD) by TSMC
- Socket AM5
- Up to sixteen Zen 4 CPU cores
- Dual-channel DDR5 memory controller
- Basic iGPU
Common features of Ryzen 7000 desktop CPUs:
- Socket: AM5.
- All the CPUs support DDR5-5200 in dual-channel mode.
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 1 MB per core.
- All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
- Includes integrated RDNA 2 GPU on the I/O die with 2 CUs and clock speeds of 400 MHz (base), 2.2 GHz (boost).[i] Models with "F" suffixes are without iGPUs.
- Fabrication process: TSMC N5 FinFET (N6 FinFET for the I/O die).
- Self identifies as "AMD Radeon Graphics". See RDNA 2 § Integrated graphics processors (iGPs).
"Phoenix" (2024)
Common features of Ryzen 8000G desktop APUs:
- Socket: AM5.
- All the CPUs support DDR5-5200 RAM in dual-channel mode in 2x1R and 2x2R configuration, but only DDR5-3600 for 4x1R and 4x2R.
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 1 MB per core.
- Models with Zen 4c cores (codenamed Phoenix 2) support 14 PCIe 4.0 lanes, while models without them support 20 lanes. 4 of the lanes are reserved as link to the chipset.
- Includes integrated RDNA 3 GPU.
- Includes XDNA AI Engine (Ryzen AI) on models without Zen 4c cores.
- Fabrication process: TSMC 4 nm FinFET.
- GPUs based on RDNA 3 have dual-issue stream processors so that up to two shader instructions can be executed per clock cycle under certain parallelism conditions.
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Server APUs
Opteron X2100-series "Kyoto" (2013) & "Steppe Eagle" (2016)
- Fabrication 28 nm
- Socket FT3 (BGA)
- 4 CPU Cores (Jaguar & Puma microarchitecture)
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
- Single-channel DDR3 memory controller
- Turbo Dock Technology, C6 and CC6 low power states
- GPU based on 2nd generation Graphics Core Next (GCN) architecture
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
Opteron X3000-series "Toronto" (2017)
- Fabrication 28 nm
- Socket FP4 (BGA)
- Two or Four CPU cores based on the Excavator microarchitecture[117][118]
- L1 Cache: 32 KB Data per core and 96 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND
- Dual-channel DDR4 memory controller
- GPU based on 3rd generation Graphics Core Next (GCN) architecture
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
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Mobile processors with 3D graphics
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APU or Radeon Graphics branded
Sabine: "Llano" (2011)
- Fabrication 32 nm on GlobalFoundries SOI process
- Socket FS1
- Upgraded Stars (AMD 10h architecture) codenamed Husky CPU cores (K10.5) with no L3 cache, and with Redwood-class integrated graphics on die
- L1 Cache: 64 KB Data per core and 64 KB Instructions per core(BeaverCreek for the dual-core variants and WinterPark for the quad-core variants)
- Integrated PCIe 2.0 controller
- GPU: TeraScale 2
- Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
- Support for 1.35 V DDR3L-1333 memory, in addition to regular 1.5 V DDR3 memory specified
- 2.5 GT/s UMI
- MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
- PowerNow!
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
Comal: "Trinity" (2012)

- Fabrication 32 nm on GlobalFoundries SOI process
- Socket FS1r2, FP2
- Based on the Piledriver architecture
- L1 Cache: 16 KB Data per core and 64 KB Instructions per module
- GPU: TeraScale 3 (VLIW4)
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
- Memory support: 1.35 V DDR3L-1600 memory, in addition to regular 1.5 V DDR3 memory specified (Dual-channel)
- 2.5 GT/s UMI
- Transistors: 1.303 billion
- Die size: 246 mm²
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
- Unified shader processors (USPs): Texture mapping units (TMUs): Render output units (ROPs). 1 CU (Compute Unit) = 64 USPs: 4 TMUs : 1 ROPs
"Richland" (2013)
- Fabrication 32 nm on GlobalFoundries SOI process
- Socket FS1r2, FP2
- Elite Performance APU.[123][124]
- CPU: Piledriver architecture
- L1 Cache: 16 KB Data per core and 64 KB Instructions per module
- GPU: TeraScale 3 (VLIW4)
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
- Unified shader processors (USPs): Texture mapping units (TMUs): Render output units (ROPs). 1 CU (Compute Unit) = 64 USPs: 4 TMUs : 1 ROPs
"Kaveri" (2014)
- Fabrication 28 nm
- Socket FP3
- Up to 4 Steamroller x86 CPU cores with 4 MB of L2 cache.[125]
- L1 Cache: 16 KB Data per core and 96 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
- Three to eight Compute Units (CUs) based on Graphics Core Next (GCN)[43] microarchitecture; 1 Compute Unit (CU) consists of 64 Unified Shader Processors : 4 Texture Mapping Units (TMUs) : 1 Render Output Unit (ROPs)
- AMD Heterogeneous System Architecture (HSA) 2.0
- SIP blocks: Unified Video Decoder, Video Coding Engine, TrueAudio[44]
- Dual-channel (2x64-bit) DDR3 memory controller
- Integrated custom ARM Cortex-A5 co-processor[45] with TrustZone Security Extensions[46]
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Carrizo" (2015)
- Fabrication 28 nm
- Socket FP4
- Up to 4 Excavator x86 CPU cores
- L1 Cache: 32 KB Data per core and 96 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
- GPU based on Graphics Core Next 1.2
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Bristol Ridge" (2016)
- Fabrication 28 nm
- Socket FP4[126]
- Two or four "Excavator+" x86 CPU cores
- L1 Cache: 32 KB Data per core and 96 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
- GPU based on Graphics Core Next 1.2 with VP9 decoding
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Raven Ridge" (2017)
- Fabrication 14 nm by GlobalFoundries
- Transistors: 4.94 billion
- Socket FP5
- Die size: 210 mm²
- Zen CPU cores
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
- Fifth generation GCN-based GPU
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Picasso" (2019)
- Fabrication 12 nm by GlobalFoundries
- Socket FP5
- Die size: 210 mm²
- Up to four Zen+ CPU cores
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
- Dual-channel DDR4 memory controller
- Fifth generation GCN-based GPU
Common features of Ryzen 3000 notebook APUs:
- Socket: FP5.
- All the CPUs support DDR4-2400 in dual-channel mode.
- L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
- L2 cache: 512 KB per core.
- All the CPUs support 16 PCIe 3.0 lanes.
- Includes integrated GCN 5th generation GPU.
- Fabrication process: GlobalFoundries 12LP (14LP+).
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Renoir" (2020)
- Fabrication 7 nm by TSMC[147][148][149]
- Socket FP6
- Die size: 156 mm²
- 9.8 billion transistors on one single 7 nm monolithic die[150]
- Up to eight Zen 2 CPU cores
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 512 KB per core.
- Fifth generation GCN-based GPU
- Memory support: DDR4-3200 or LPDDR4-4266 in dual-channel mode.
- All the CPUs support 16 PCIe 3.0 lanes.
U
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
H
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Lucienne" (2021)
- Fabrication 7 nm by TSMC
- Socket FP6
- Die size: 156 mm²
- 9.8 billion transistors on one single 7 nm monolithic die[citation needed]
- Up to eight Zen 2 CPU cores
- Fifth generation GCN-based GPU (7 nm Vega)
Common features of Ryzen 5000 notebook APUs:
- Socket: FP6.
- All the CPUs support DDR4-3200 or LPDDR4-4266 in dual-channel mode.
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 512 KB per core.
- All the CPUs support 16 PCIe 3.0 lanes.
- Includes integrated GCN 5th generation GPU.
- Fabrication process: TSMC 7FF.
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Cezanne" (2021)
- Fabrication 7 nm by TSMC
- Socket FP6
- Die size: 180 mm²
- Up to eight Zen 3 CPU cores
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 512 KB per core.
- Fifth generation GCN-based GPU
- Memory support: DDR4-3200 or LPDDR4-4266 in dual-channel mode.
- All the CPUs support 16 PCIe 3.0 lanes.
U
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
H
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Barceló" (2022)
- Fabrication 7 nm by TSMC
- Socket FP6
- Die size: 180 mm²
- Up to eight Zen 3 CPU cores
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 512 KB per core.
- Fifth generation GCN-based GPU
- Memory support: DDR4-3200 or LPDDR4-4266 in dual-channel mode.
- All the CPUs support 16 PCIe 3.0 lanes.
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Rembrandt" (2022)
- Fabrication 6 nm by TSMC
- Socket FP7
- Die size: 210 mm²
- Up to eight Zen 3+ CPU cores
- Second generation RDNA-based GPU
Common features of Ryzen 6000 notebook APUs:
- Socket: FP7, FP7r2.
- All the CPUs support DDR5-4800 or LPDDR5-6400 in dual-channel mode.
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 512 KB per core.
- All the CPUs support 16 PCIe 4.0 lanes.
- Native USB 4 (40Gbps) Ports: 2
- Native USB 3.2 Gen 2 (10Gbps) Ports: 2
- Includes integrated RDNA 2 GPU.
- Fabrication process: TSMC N6 FinFET.
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Phoenix" (2023)
- Fabrication 4 nm by TSMC
- Up to eight Zen 4 CPU cores
- Dual-channel DDR5 or LPDDR5x memory controller
- RDNA3 iGPU
- XDNA accelerator
"Dragon Range" (2023)
- Fabrication 5 nm (CCD) and 6 nm (cIOD) by TSMC
- Up to sixteen Zen 4 CPU cores
- Dual-channel DDR5 memory controller
- Basic RDNA2 iGPU
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Ultra-mobile APUs
Summarize
Perspective
Brazos: "Desna", "Ontario", "Zacate" (2011)
- Fabrication 40 nm by TSMC
- Socket FT1 (BGA-413)
- Based on the Bobcat microarchitecture[191]
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
- PowerNow!
- DirectX 11 integrated graphics with UVD 3.0
- Z-series denote Desna; C-series denote Ontario; and the E-series denotes Zacate
- 2.50 GT/s UMI (PCIe 1.0 ×4)
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
Brazos 2.0: "Ontario", "Zacate" (2012)
- Fabrication 40 nm by TSMC
- Socket FT1 (BGA-413)
- Based on the Bobcat microarchitecture[191]
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
- PowerNow!
- DirectX 11 integrated graphics
- C-series denote Ontario; and the E-series denotes Zacate
- 2.50 GT/s UMI (PCIe 1.0 ×4)
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
Brazos-T: "Hondo" (2012)
- Fabrication 40 nm by TSMC
- Socket FT1 (BGA-413)
- Based on the Bobcat microarchitecture[191]
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- Found in tablet computers
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
- PowerNow!
- DirectX 11 integrated graphics
- 2.50 GT/s UMI (PCIe 1.0 ×4)
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Kabini", "Temash" (2013)
- Fabrication 28 nm by TSMC
- Socket FT3 (BGA)
- 2 to 4 CPU Cores (Jaguar (microarchitecture))
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
- Turbo Dock Technology, C6 and CC6 low power states
- GPU based on Graphics Core Next (GCN)
- AMD Eyefinity multi-monitor for up to two displays
Temash, Elite Mobility APU
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
Kabini, Mainstream APU
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
"Beema", "Mullins" (2014)
- Fabrication 28 nm by GlobalFoundries
- Socket FT3b (BGA)
- CPU: 2 to 4 (Puma cores)
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- GPU based on Graphics Core Next (GCN)
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
- Intelligent Turbo Boost
- Platform Security Processor, with an integrated ARM Cortex-A5 for TrustZone execution
Mullins, Tablet/2-in-1 APU
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
Beema, Notebook APU
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
"Carrizo-L" (2015)
- Fabrication 28 nm by GlobalFoundries
- Socket FT3b (BGA), FP4 (μBGA)[194]
- CPU: 2 to 4 (Puma+ cores)
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- GPU based on Graphics Core Next (GCN)
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
- Intelligent Turbo Boost
- Platform Security Processor, with an integrated ARM Cortex-A5 for TrustZone execution
- All models except A8-7410 available in both laptop and all-in-one desktop versions
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
"Stoney Ridge" (2016)
- Fabrication 28 nm by GlobalFoundries
- Socket FP4[126] / FT4
- 2 "Excavator+" x86 CPU cores
- L1 Cache: 32 KB Data per core and 96 KB Instructions per module
- Single-channel DDR4 memory controller
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
- GPU based on Graphics Core Next 3rd Generation with VP9 decoding
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Dalí" (2020)
- Fabrication 14 nm by GlobalFoundries
- Socket FP5
- Two Zen CPU cores
- Over 30% die size reduction over predecessor (Raven Ridge)
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
- Dual-channel RAM
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Pollock" (2020)
- Fabrication 14 nm by GlobalFoundries
- Socket FT5
- Two Zen CPU cores
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
- Single-channel RAM
- Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Mendocino" (2022)
Common features:
- Socket: FT6
- All the CPUs support LPDDR5-5500 in dual-channel mode.
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 512 KB per core.
- All the CPUs support 4 PCIe 3.0 lanes.
- Includes integrated RDNA2 GPU.
- Fabrication process: TSMC 6 nm FinFET.
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Embedded APUs
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Perspective
G-Series
Brazos: "Ontario" and "Zacate" (2011)
- Fabrication 40 nm
- Socket FT1 (BGA-413)
- CPU microarchitecture: Bobcat[202]
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
- GPU microarchitecture: TeraScale 2 (VLIW5) "Evergreen"
- Memory support: single-channel, support up to two DIMMs of DDR3-1333 or DDR3L-1066
- 5 GT/s UMI
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Kabini" (2013, SoC)
- Fabrication 28 nm
- Socket FT3 (769-BGA)[203]
- CPU microarchitecture: Jaguar
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support. No support for FMA (Fused Multiply-Accumulate). Trusted Platform Module (TPM) 1.2 support
- GPU microarchitecture: Graphics Core Next (GCN) with Unified Video Decoder 3 (H.264, VC-1, MPEG2, etc.)
- Single channel DDR3-1600, 1.25 and 1.35 V voltage level support, support for ECC memory
- Integrates Controller Hub functional block, HD audio, 2 SATA channels, USB 2.0 and USB 3.0 (except GX-210JA)
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Steppe Eagle" (2014, SoC)
- Fabrication 28 nm
- Socket FT3b (769-BGA)
- CPU microarchitecture: Puma
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Crowned Eagle" (2014, SoC)
- Fabrication 28 nm
- Socket FT3b (769-BGA)
- CPU microarchitecture: Puma
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
- no GPU
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
LX-Family (2016, SoC)
- Fabrication 28 nm
- Socket FT3b (769-BGA)
- 2 Puma x86 cores with 1MB shared L2 cache
- L1 Cache: 32 KB Data per core and 32 KB Instructions per core
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
- GPU microarchitecture: Graphics Core Next (GCN) (1CU) with support for DirectX 11.2
- Single channel 64-bit DDR3 memory with ECC
- Integrated Controller Hub supports: PCIe® 2.0 4×1, 2 USB3 + 4 USB2 ports, 2 SATA 2.0/3.0 ports
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
I-Family: "Brown Falcon" (2016, SoC)
- Fabrication 28 nm
- Socket FP4[204]
- 2 or 4 Excavator x86 cores with 1MB shared L2 cache
- L1 Cache: 32 KB Data per core and 96 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND
- GPU microarchitecture: Graphics Core Next (GCN) (up to 4 CUs) with support for DirectX 12
- Dual channel 64-bit DDR4 or DDR3 memory with ECC
- 4K × 2K H.265 decode capability and multi format encode and decode
- Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
J-Family: "Prairie Falcon" (2016, SoC)
- Fabrication 28 nm
- Socket FP4[206]
- 2 "Excavator+" x86 cores with 1MB shared L2 cache
- L1 Cache: 32 KB Data per core and 96 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND
- GPU microarchitecture: Radeon R5E Graphics Core Next (GCN) (up to 3 CUs) with support for DirectX 12
- Single channel 64-bit DDR4 or DDR3 memory
- 4K × 2K H.265 decode capability with 10-bit compatibility and multi format encode and decode
- Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
R-Series
Comal: "Trinity" (2012)
- Fabrication 32 nm
- Socket FP2 (BGA-827), FS1r2
- CPU microarchitecture: Piledriver
- L1 Cache: 16 KB Data per core and 64 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX 1.1, XOP, FMA3, FMA4, F16C,[29] ABM, BMI1, TBM
- GPU microarchitecture: TeraScale 3 (VLIW4) "Northern Islands"
- Memory support: dual-channel 1.35 V DDR3L-1600 memory, in addition to regular 1.5 V DDR3
- 2.5 GT/s UMI
- Die size: 246 mm²; Transistors: 1.303 billion
- OpenCL 1.1 and OpenGL 4.2 support
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Bald Eagle" (2014)
- Fabrication 28 nm
- Socket FP3
- Up to 4 Steamroller x86 cores[207]
- L1 Cache: 16 KB Data per core and 96 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX 1.1, XOP, FMA3, FMA4, F16C,[29] ABM, BMI1, TBM
- GPU microarchitecture: Graphics Core Next (GCN) (up to 8 CUs) with support for DirectX 11.1 and OpenGL 4.2
- Dual channel DDR3 memory with ECC
- Unified Video Decode (UVD) 4.2 and Video Coding Engine (VCE) 2.0
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
"Merlin Falcon" (2015, SoC)
- Fabrication 28 nm
- Socket FP4
- Up to 4 Excavator x86 cores[208]
- L1 Cache: 32 KB Data per core and 96 KB Instructions per module
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND
- GPU microarchitecture: Graphics Core Next (GCN) (up to 8 CUs) with support for DirectX 12
- Dual channel 64-bit DDR4 or DDR3 memory with ECC
- Unified Video Decode (UVD) 6 (4K H.265 and H.264 decode) and Video Coding Engine (VCE) 3.1 (4K H.264 encode)
- Dedicated AMD Secure Processor supports secure boot with AMD Hardware Validated Boot (HVB)
- Integrated FCH featuring PCIe 3.0 USB3.0, SATA3, SD, GPIO, SPI, I2S, I2C, UART
- AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[27]
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
1000-Series
V1000-Family: "Great Horned Owl" (2018, SoC)
- Fabrication 14 nm by GlobalFoundries
- Up to 4 Zen cores
- Socket FP5
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
- Dual channel DDR4 memory with ECC
- Fifth generation GCN based GPU
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
R1000-Family: "Banded Kestrel" (2019, SoC)
- Fabrication 14 nm by GlobalFoundries
- Up to 2 Zen cores
- Socket FP5
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
- Dual channel DDR4 memory with ECC
- Fifth generation GCN based GPU
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
2000-Series
V2000-Family: "Grey Hawk" (2020, SoC)
- Fabrication 7 nm by TSMC
- Up to 8 Zen 2 cores
- Fifth generation GCN based GPU
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
R2000-Family: "River Hawk" (2022, SoC)
- Fabrication 12 nm by GlobalFoundries
- Up to 4 Zen+ cores
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
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Custom APUs
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Perspective
As of May 1, 2013, AMD opened the doors of their "semi-custom" business unit.[213] Since these chips are custom-made for specific customer needs, they vary widely from both consumer-grade APUs and even the other custom-built ones. Some notable examples of semi-custom chips that have come from this sector include the chips from the PlayStation 4 and Xbox One.[214] So far the size of the integrated GPU in these semi-custom APUs exceed by far the GPU size in the consumer-grade APUs.
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See also
Notes
- Unified shader processors (USPs): Texture mapping units (TMUs): Render output units (ROPs). 1 CU (Compute Unit) = 64 USPs: 4 TMUs : 1 ROPs
References
External links
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