RISC-V

RISC-V[lower-alpha 2] (pronounced "risk-five",[1]^: 1) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. A number of companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.

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RISC-V

Designer	University of California, Berkeley
Bits	32, 64, 128
Introduced	2015; 8 years ago (2015)
Version	unprivileged ISA 20191213,[1] privileged ISA 20211203[2]
Design	RISC
Type	Load-store
Encoding	Variable
Branching	Compare-and-branch
Endianness	Little[1]: 9 [lower-alpha 1]
Page size	4 KiB
Extensions	M: Multiplication A: Atomics – LR/SC & fetch-and-op F: Floating point (32-bit) D: FP Double (64-bit) Q: FP Quad (128-bit) Zicsr: Control and status register support Zifencei: Load/store fence C: Compressed instructions (16-bit) J: Interpreted or JIT-compiled languages support
Open	Yes, royalty free
Registers
General-purpose	16 32 (Includes one always-zero register)
Floating point	32 (Optional. Width depends on available extensions)

As a RISC architecture, the RISC-V ISA is a load–store architecture. Its floating-point instructions use IEEE 754 floating-point. Notable features of the RISC-V ISA include: instruction bit field locations chosen to simplify the use of multiplexers in a CPU,[1]^: 17 a design that is architecturally neutral, and a fixed location for the sign bit of immediate values to speed up sign extension.[1]^: 17

The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction can be any number of 16-bit parcels in length.[1]^: 7–10 Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.

The instruction set specification defines 32-bit and 64-bit address space variants. The specification includes a description of a 128-bit flat address space variant, as an extrapolation of 32 and 64 bit variants, but the 128-bit ISA remains "not frozen" intentionally, because there is yet so little practical experience with such large memory systems.[1]^: 41

Unlike other academic designs which are typically optimized only for simplicity of exposition, the designers intended that the RISC-V instruction set be usable for practical computers. As of June 2019, version 2.2 of the user-space ISA[4] and version 1.11 of the privileged ISA[2] are frozen, permitting software and hardware development to proceed. The user-space ISA, now renamed the Unprivileged ISA, was updated, ratified and frozen as version 20191213.[1] An external debug specification is available as a draft, version 0.13.2.[5]

The project began in 2010 at the University of California, Berkeley, but now many current contributors are volunteers not affiliated with the university.[6] With members over 70 countries contribute and collaborate to define RISC-V open specifications, the RISC-V International is currently headquartered in politically neutral Switzerland.[7][8]